[PATCH] D52970: [X86][AVX2] Enable ZERO_EXTEND_VECTOR_INREG lowering of 256-bit vectors

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: test/CodeGen/X86/pr35443.ll:18
 entry:
   %wide.masked.load66 = call <4 x i8> @llvm.masked.load.v4i8.p0v4i8(<4 x i8>* bitcast (i8* getelementptr inbounds ([20 x i8], [20 x i8]* @ac, i64 0, i64 4) to <4 x i8>*), i32 1, <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i8> undef)
   %0 = zext <4 x i8> %wide.masked.load66 to <4 x i64>
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RKSimon wrote:
> @craig.topper Please can you confirm if the pr35443.ll change is acceptable?
> 
> An alternative is to set the passthrough value zeroinitializer, which instead adds a vpmovzxbq op after the vmovd (some kind of demanded bits failure that could be fixed in a future patch).
What if you just change the alignment of @ac to 1? That should prevent the single byte load from the masked.load from promoting to a wider size I think.


Repository:
  rL LLVM

https://reviews.llvm.org/D52970