[PATCH] D52846: [AMDGPU] Add FixupVectorISel pass, currently Supports SREGs in GLOBAL LD/ST

[Ron Lieberman via Phabricator via llvm-commits]

ronlieb updated this revision to Diff 168576.
ronlieb added a comment.

added a load/store globals test case (.mir)
updated global-saddr-misc.ll per offline discussion.
changed assert to  simpler if (check) continue.


https://reviews.llvm.org/D52846

Files:
  lib/Target/AMDGPU/AMDGPU.h
  lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
  lib/Target/AMDGPU/CMakeLists.txt
  lib/Target/AMDGPU/FLATInstructions.td
  lib/Target/AMDGPU/SIFixupVectorISel.cpp
  lib/Target/AMDGPU/SIInstrInfo.h
  lib/Target/AMDGPU/SIInstrInfo.td
  test/CodeGen/AMDGPU/conv2d-saddr.ll
  test/CodeGen/AMDGPU/ds_write2.ll
  test/CodeGen/AMDGPU/ds_write2st64.ll
  test/CodeGen/AMDGPU/global-load_stores.mir
  test/CodeGen/AMDGPU/global-saddr-atomics.ll
  test/CodeGen/AMDGPU/global-saddr-misc.ll
  test/CodeGen/AMDGPU/global-saddr-offsets.ll
  test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
  test/CodeGen/AMDGPU/insert_vector_elt.v2i16.subtest-nosaddr.ll
  test/CodeGen/AMDGPU/insert_vector_elt.v2i16.subtest-saddr.ll
  test/CodeGen/AMDGPU/madak.ll
  test/CodeGen/AMDGPU/memory-legalizer-load.ll
  test/CodeGen/AMDGPU/memory-legalizer-store.ll
  test/CodeGen/AMDGPU/memory_clause.ll
  test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll

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