[PATCH] D52846: [AMDGPU] Add FixupVectorISel pass, currently Supports SREGs in GLOBAL LD/ST

[Ron Lieberman via Phabricator via llvm-commits]

ronlieb added a comment.

I am planning to add another lit test for coverage of all the Global load/store opcodes.



================
Comment at: lib/Target/AMDGPU/SIFixupVectorISel.cpp:101
+    case AMDGPU::REG_SEQUENCE:
+      assert(DefInst->getNumOperands() == 5 && "Unexpected REQ_SEQUENCE");
+      Worklist.push_back(&DefInst->getOperand(1));
----------------
assert seems like overkill, so I am going to change this to
if (DefInst->getNumOperands() != 5)
  continue;



================
Comment at: test/CodeGen/AMDGPU/global-saddr-misc.ll:10
+.entry:
+  %tmp9 = add <3 x i32> %arg3, %arg5
+  %tmp10 = extractelement <3 x i32> %tmp9, i32 0
----------------
Reduced version of this test in the works, next patch rev.


https://reviews.llvm.org/D52846