[PATCH] D52779: AMD BdVer2 (Piledriver) Initial Scheduler model

[Clement Courbet via Phabricator via llvm-commits]

courbet added a comment.

This is awesome !

In https://reviews.llvm.org/D52779#1252458, @lebedev.ri wrote:

> - *Many* of the inconsistencies are noise
> - fp measurements are flaky
> - Non-fp measurements are somewhat flaky too


Part of the flakiness can be explained by zero idioms: since llvm-exegesis explores register allocation randomly, it will hit some zero idioms by chance (and you've hit it e.g. for SUB32rr). Analysis still does not handle variant classes (PR38884), and we need better highlighting of instances where mcinst predicates were true. I'm currently working on this.

I'll have a look at the inconsistencies to see if I can see anything else that might be an analysis issue.


Repository:
  rL LLVM

https://reviews.llvm.org/D52779