[PATCH] D52779: AMD BdVer2 (Piledriver) Initial Scheduler model

Roman Lebedev via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Oct 2 06:51:12 PDT 2018


lebedev.ri updated this revision to Diff 167937.
lebedev.ri edited the summary of this revision.
lebedev.ri added reviewers: RKSimon, andreadb, courbet, avt77, spatel.
lebedev.ri added a comment.

I fat-fingered it, re-uploading so the actual description is in place.

This is somewhat partial.
Overview:

- Latencies are reasonably-good F7345689: clusters-latency-0.5eps.html <https://reviews.llvm.org/F7345689>
  - There are still some inconsistencies.
  - *Many* of the inconsistencies are noise
  - fp measurements are flaky
  - Non-fp measurements are somewhat flaky too
- NumMicroOps are somewhat good F7345689: clusters-latency-0.5eps.html <https://reviews.llvm.org/F7345689>
  - Most of the remaining inconsistencies are from `Ld` / `Ld_ReadAfterLd` classes
- Actual unit occupation (pipes, `ResourceCycles`) are undiscovered lands, i did not really look there. They are basically verbatum copy from `btver2`
- Many `InstRW`. And there are still inconsistencies left...

What's not here:

- llvm-mca test coverage. I understand how to not just add the coverage here, but actually show a diff, but i did not look there yet.
- benchmarks. I'd say it's too soon for any measurements.

To be noted:
I think this is the first new schedule profile produced with the new next-gen tools like llvm-exegesis!

llvm-exegesis details:
F7345685: benchmarks-latency-100000rep.yaml <https://reviews.llvm.org/F7345685>

F7345686: benchmarks-alluops-100000rep.yaml <https://reviews.llvm.org/F7345686>

F7345687: benchmarks-nummicroops-100000rep.yaml <https://reviews.llvm.org/F7345687>

F7345689: clusters-latency-0.5eps.html <https://reviews.llvm.org/F7345689>

F7345690: clusters-nummicroops-0.5eps.html <https://reviews.llvm.org/F7345690>


Repository:
  rL LLVM

https://reviews.llvm.org/D52779

Files:
  lib/Target/X86/X86.td
  lib/Target/X86/X86PfmCounters.td
  lib/Target/X86/X86ScheduleBdVer2.td
  test/CodeGen/X86/fma.ll
  test/CodeGen/X86/lwp-intrinsics.ll
  test/CodeGen/X86/lwp-schedule.ll
  test/CodeGen/X86/tbm-schedule.ll
  test/CodeGen/X86/wide-fma-contraction.ll

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