[PATCH] D52736: [AMDGPU] Fixed SIInstrInfo::getOpSize to handle subregs
Matt Arsenault via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 1 19:13:16 PDT 2018
arsenm added inline comments.
================
Comment at: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h:735-736
+ if (MO.isReg()) {
+ if (unsigned SubReg = MO.getSubReg())
+ return RI.getSubRegIndexLaneMask(SubReg).getNumLanes() * 4;
+ }
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I think this silently will break if we start using 16-bit subregs. Can you assert that this number is consistent with the size of the super-reg?
Repository:
rL LLVM
https://reviews.llvm.org/D52736
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