[PATCH] D52736: [AMDGPU] Fixed SIInstrInfo::getOpSize to handle subregs

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL343508: [AMDGPU] Fixed SIInstrInfo::getOpSize to handle subregs (authored by rampitec, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D52736?vs=167771&id=167780#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D52736

Files:
  llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h


Index: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h
@@ -730,6 +730,11 @@
   /// This form should usually be preferred since it handles operands
   /// with unknown register classes.
   unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const {
+    const MachineOperand &MO = MI.getOperand(OpNo);
+    if (MO.isReg()) {
+      if (unsigned SubReg = MO.getSubReg())
+        return RI.getSubRegIndexLaneMask(SubReg).getNumLanes() * 4;
+    }
     return RI.getRegSizeInBits(*getOpRegClass(MI, OpNo)) / 8;
   }
 


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