[llvm] r343311 - [X86][Btver2] Fix BSF/BSR schedule
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 28 03:26:48 PDT 2018
Author: rksimon
Date: Fri Sep 28 03:26:48 2018
New Revision: 343311
URL: http://llvm.org/viewvc/llvm-project?rev=343311&view=rev
Log:
[X86][Btver2] Fix BSF/BSR schedule
Double throughput to account for 2 pipes + fix BSF's latency/uop counts
Match AMD Fam16h SOG + llvm-exegesis tests
Modified:
llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
llvm/trunk/test/CodeGen/X86/schedule-x86_64.ll
llvm/trunk/test/tools/llvm-mca/X86/BtVer2/clear-super-register-1.s
llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-x86_64.s
Modified: llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td?rev=343311&r1=343310&r2=343311&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td Fri Sep 28 03:26:48 2018
@@ -208,8 +208,8 @@ defm : X86WriteRes<WriteBitTestSet, [JAL
def : WriteRes<WriteLEA, [JALU01]>;
// Bit counts.
-defm : JWriteResIntPair<WriteBSF, [JALU01], 5, [4], 8>;
-defm : JWriteResIntPair<WriteBSR, [JALU01], 5, [4], 8>;
+defm : JWriteResIntPair<WriteBSF, [JALU01], 4, [8], 7>;
+defm : JWriteResIntPair<WriteBSR, [JALU01], 5, [8], 8>;
defm : JWriteResIntPair<WritePOPCNT, [JALU01], 1>;
defm : JWriteResIntPair<WriteLZCNT, [JALU01], 1>;
defm : JWriteResIntPair<WriteTZCNT, [JALU01], 2, [2], 2>;
Modified: llvm/trunk/test/CodeGen/X86/schedule-x86_64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/schedule-x86_64.ll?rev=343311&r1=343310&r2=343311&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/schedule-x86_64.ll (original)
+++ llvm/trunk/test/CodeGen/X86/schedule-x86_64.ll Fri Sep 28 03:26:48 2018
@@ -2024,8 +2024,8 @@ define i16 @test_bsf16(i16 %a0, i16* %a1
; BTVER2-LABEL: test_bsf16:
; BTVER2: # %bb.0:
; BTVER2-NEXT: #APP
-; BTVER2-NEXT: bsfw %di, %ax # sched: [5:2.00]
-; BTVER2-NEXT: bsfw (%rsi), %cx # sched: [8:2.00]
+; BTVER2-NEXT: bsfw %di, %ax # sched: [4:4.00]
+; BTVER2-NEXT: bsfw (%rsi), %cx # sched: [7:4.00]
; BTVER2-NEXT: #NO_APP
; BTVER2-NEXT: orl %ecx, %eax # sched: [1:0.50]
; BTVER2-NEXT: # kill: def $ax killed $ax killed $eax
@@ -2122,8 +2122,8 @@ define i32 @test_bsf32(i32 %a0, i32* %a1
; BTVER2-LABEL: test_bsf32:
; BTVER2: # %bb.0:
; BTVER2-NEXT: #APP
-; BTVER2-NEXT: bsfl %edi, %eax # sched: [5:2.00]
-; BTVER2-NEXT: bsfl (%rsi), %ecx # sched: [8:2.00]
+; BTVER2-NEXT: bsfl %edi, %eax # sched: [4:4.00]
+; BTVER2-NEXT: bsfl (%rsi), %ecx # sched: [7:4.00]
; BTVER2-NEXT: #NO_APP
; BTVER2-NEXT: orl %ecx, %eax # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00]
@@ -2218,8 +2218,8 @@ define i64 @test_bsf64(i64 %a0, i64* %a1
; BTVER2-LABEL: test_bsf64:
; BTVER2: # %bb.0:
; BTVER2-NEXT: #APP
-; BTVER2-NEXT: bsfq %rdi, %rax # sched: [5:2.00]
-; BTVER2-NEXT: bsfq (%rsi), %rcx # sched: [8:2.00]
+; BTVER2-NEXT: bsfq %rdi, %rax # sched: [4:4.00]
+; BTVER2-NEXT: bsfq (%rsi), %rcx # sched: [7:4.00]
; BTVER2-NEXT: #NO_APP
; BTVER2-NEXT: orq %rcx, %rax # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00]
@@ -2323,8 +2323,8 @@ define i16 @test_bsr16(i16 %a0, i16* %a1
; BTVER2-LABEL: test_bsr16:
; BTVER2: # %bb.0:
; BTVER2-NEXT: #APP
-; BTVER2-NEXT: bsrw %di, %ax # sched: [5:2.00]
-; BTVER2-NEXT: bsrw (%rsi), %cx # sched: [8:2.00]
+; BTVER2-NEXT: bsrw %di, %ax # sched: [5:4.00]
+; BTVER2-NEXT: bsrw (%rsi), %cx # sched: [8:4.00]
; BTVER2-NEXT: #NO_APP
; BTVER2-NEXT: orl %ecx, %eax # sched: [1:0.50]
; BTVER2-NEXT: # kill: def $ax killed $ax killed $eax
@@ -2421,8 +2421,8 @@ define i32 @test_bsr32(i32 %a0, i32* %a1
; BTVER2-LABEL: test_bsr32:
; BTVER2: # %bb.0:
; BTVER2-NEXT: #APP
-; BTVER2-NEXT: bsrl %edi, %eax # sched: [5:2.00]
-; BTVER2-NEXT: bsrl (%rsi), %ecx # sched: [8:2.00]
+; BTVER2-NEXT: bsrl %edi, %eax # sched: [5:4.00]
+; BTVER2-NEXT: bsrl (%rsi), %ecx # sched: [8:4.00]
; BTVER2-NEXT: #NO_APP
; BTVER2-NEXT: orl %ecx, %eax # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00]
@@ -2517,8 +2517,8 @@ define i64 @test_bsr64(i64 %a0, i64* %a1
; BTVER2-LABEL: test_bsr64:
; BTVER2: # %bb.0:
; BTVER2-NEXT: #APP
-; BTVER2-NEXT: bsrq %rdi, %rax # sched: [5:2.00]
-; BTVER2-NEXT: bsrq (%rsi), %rcx # sched: [8:2.00]
+; BTVER2-NEXT: bsrq %rdi, %rax # sched: [5:4.00]
+; BTVER2-NEXT: bsrq (%rsi), %rcx # sched: [8:4.00]
; BTVER2-NEXT: #NO_APP
; BTVER2-NEXT: orq %rcx, %rax # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00]
Modified: llvm/trunk/test/tools/llvm-mca/X86/BtVer2/clear-super-register-1.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/tools/llvm-mca/X86/BtVer2/clear-super-register-1.s?rev=343311&r1=343310&r2=343311&view=diff
==============================================================================
--- llvm/trunk/test/tools/llvm-mca/X86/BtVer2/clear-super-register-1.s (original)
+++ llvm/trunk/test/tools/llvm-mca/X86/BtVer2/clear-super-register-1.s Fri Sep 28 03:26:48 2018
@@ -15,13 +15,13 @@ bsf %rax, %rcx
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 400
-# CHECK-NEXT: Total Cycles: 704
-# CHECK-NEXT: Total uOps: 1200
+# CHECK-NEXT: Total Cycles: 656
+# CHECK-NEXT: Total uOps: 1100
# CHECK: Dispatch Width: 2
-# CHECK-NEXT: uOps Per Cycle: 1.70
-# CHECK-NEXT: IPC: 0.57
-# CHECK-NEXT: Block RThroughput: 6.0
+# CHECK-NEXT: uOps Per Cycle: 1.68
+# CHECK-NEXT: IPC: 0.61
+# CHECK-NEXT: Block RThroughput: 5.5
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
@@ -35,20 +35,20 @@ bsf %rax, %rcx
# CHECK-NEXT: 2 6 4.00 imulq $5, %rcx, %rax
# CHECK-NEXT: 1 1 0.50 lzcntl %ecx, %eax
# CHECK-NEXT: 1 1 0.50 andq %rcx, %rax
-# CHECK-NEXT: 8 5 2.00 bsfq %rax, %rcx
+# CHECK-NEXT: 7 4 4.00 bsfq %rax, %rcx
# CHECK: Timeline view:
-# CHECK-NEXT: 01234567
+# CHECK-NEXT: 0123456
# CHECK-NEXT: Index 0123456789
-# CHECK: [0,0] DeeeeeeER . . . imulq $5, %rcx, %rax
-# CHECK-NEXT: [0,1] .DeE----R . . . lzcntl %ecx, %eax
-# CHECK-NEXT: [0,2] .D=eE----R. . . andq %rcx, %rax
-# CHECK-NEXT: [0,3] . D=eeeeeER . . bsfq %rax, %rcx
-# CHECK-NEXT: [1,0] . .D==eeeeeeER. imulq $5, %rcx, %rax
-# CHECK-NEXT: [1,1] . . D=eE-----R. lzcntl %ecx, %eax
-# CHECK-NEXT: [1,2] . . D==eE-----R andq %rcx, %rax
-# CHECK-NEXT: [1,3] . . D==eeeeeER bsfq %rax, %rcx
+# CHECK: [0,0] DeeeeeeER . .. imulq $5, %rcx, %rax
+# CHECK-NEXT: [0,1] .DeE----R . .. lzcntl %ecx, %eax
+# CHECK-NEXT: [0,2] .D=eE----R. .. andq %rcx, %rax
+# CHECK-NEXT: [0,3] . D=eeeeER. .. bsfq %rax, %rcx
+# CHECK-NEXT: [1,0] . .D=eeeeeeER. imulq $5, %rcx, %rax
+# CHECK-NEXT: [1,1] . . D=eE----R. lzcntl %ecx, %eax
+# CHECK-NEXT: [1,2] . . D==eE----R andq %rcx, %rax
+# CHECK-NEXT: [1,3] . . D==eeeeER bsfq %rax, %rcx
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -57,7 +57,7 @@ bsf %rax, %rcx
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
-# CHECK-NEXT: 0. 2 2.0 0.5 0.0 imulq $5, %rcx, %rax
-# CHECK-NEXT: 1. 2 1.5 0.5 4.5 lzcntl %ecx, %eax
-# CHECK-NEXT: 2. 2 2.5 0.0 4.5 andq %rcx, %rax
+# CHECK-NEXT: 0. 2 1.5 0.5 0.0 imulq $5, %rcx, %rax
+# CHECK-NEXT: 1. 2 1.5 1.0 4.0 lzcntl %ecx, %eax
+# CHECK-NEXT: 2. 2 2.5 0.0 4.0 andq %rcx, %rax
# CHECK-NEXT: 3. 2 2.5 0.0 0.0 bsfq %rax, %rcx
Modified: llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-x86_64.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-x86_64.s?rev=343311&r1=343310&r2=343311&view=diff
==============================================================================
--- llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-x86_64.s (original)
+++ llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-x86_64.s Fri Sep 28 03:26:48 2018
@@ -951,18 +951,18 @@ xorq (%rax), %rdi
# CHECK-NEXT: 1 1 0.50 andq %rsi, %rdi
# CHECK-NEXT: 2 5 1.00 * * andq %rsi, (%rax)
# CHECK-NEXT: 1 4 1.00 * andq (%rax), %rdi
-# CHECK-NEXT: 8 5 2.00 bsfw %si, %di
-# CHECK-NEXT: 8 5 2.00 bsrw %si, %di
-# CHECK-NEXT: 8 8 2.00 * bsfw (%rax), %di
-# CHECK-NEXT: 8 8 2.00 * bsrw (%rax), %di
-# CHECK-NEXT: 8 5 2.00 bsfl %esi, %edi
-# CHECK-NEXT: 8 5 2.00 bsrl %esi, %edi
-# CHECK-NEXT: 8 8 2.00 * bsfl (%rax), %edi
-# CHECK-NEXT: 8 8 2.00 * bsrl (%rax), %edi
-# CHECK-NEXT: 8 5 2.00 bsfq %rsi, %rdi
-# CHECK-NEXT: 8 5 2.00 bsrq %rsi, %rdi
-# CHECK-NEXT: 8 8 2.00 * bsfq (%rax), %rdi
-# CHECK-NEXT: 8 8 2.00 * bsrq (%rax), %rdi
+# CHECK-NEXT: 7 4 4.00 bsfw %si, %di
+# CHECK-NEXT: 8 5 4.00 bsrw %si, %di
+# CHECK-NEXT: 7 7 4.00 * bsfw (%rax), %di
+# CHECK-NEXT: 8 8 4.00 * bsrw (%rax), %di
+# CHECK-NEXT: 7 4 4.00 bsfl %esi, %edi
+# CHECK-NEXT: 8 5 4.00 bsrl %esi, %edi
+# CHECK-NEXT: 7 7 4.00 * bsfl (%rax), %edi
+# CHECK-NEXT: 8 8 4.00 * bsrl (%rax), %edi
+# CHECK-NEXT: 7 4 4.00 bsfq %rsi, %rdi
+# CHECK-NEXT: 8 5 4.00 bsrq %rsi, %rdi
+# CHECK-NEXT: 7 7 4.00 * bsfq (%rax), %rdi
+# CHECK-NEXT: 8 8 4.00 * bsrq (%rax), %rdi
# CHECK-NEXT: 1 1 0.50 bswapl %eax
# CHECK-NEXT: 1 1 0.50 bswapq %rax
# CHECK-NEXT: 1 1 0.50 btw %si, %di
@@ -1626,7 +1626,7 @@ xorq (%rax), %rdi
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
-# CHECK-NEXT: 557.50 607.50 380.00 - - - - 319.00 64.00 223.00 - - - -
+# CHECK-NEXT: 581.50 631.50 380.00 - - - - 319.00 64.00 223.00 - - - -
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] Instructions:
@@ -1720,18 +1720,18 @@ xorq (%rax), %rdi
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - andq %rsi, %rdi
# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - 1.00 - - - - andq %rsi, (%rax)
# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - - andq (%rax), %rdi
-# CHECK-NEXT: 2.00 2.00 - - - - - - - - - - - - bsfw %si, %di
-# CHECK-NEXT: 2.00 2.00 - - - - - - - - - - - - bsrw %si, %di
-# CHECK-NEXT: 2.00 2.00 - - - - - 1.00 - - - - - - bsfw (%rax), %di
-# CHECK-NEXT: 2.00 2.00 - - - - - 1.00 - - - - - - bsrw (%rax), %di
-# CHECK-NEXT: 2.00 2.00 - - - - - - - - - - - - bsfl %esi, %edi
-# CHECK-NEXT: 2.00 2.00 - - - - - - - - - - - - bsrl %esi, %edi
-# CHECK-NEXT: 2.00 2.00 - - - - - 1.00 - - - - - - bsfl (%rax), %edi
-# CHECK-NEXT: 2.00 2.00 - - - - - 1.00 - - - - - - bsrl (%rax), %edi
-# CHECK-NEXT: 2.00 2.00 - - - - - - - - - - - - bsfq %rsi, %rdi
-# CHECK-NEXT: 2.00 2.00 - - - - - - - - - - - - bsrq %rsi, %rdi
-# CHECK-NEXT: 2.00 2.00 - - - - - 1.00 - - - - - - bsfq (%rax), %rdi
-# CHECK-NEXT: 2.00 2.00 - - - - - 1.00 - - - - - - bsrq (%rax), %rdi
+# CHECK-NEXT: 4.00 4.00 - - - - - - - - - - - - bsfw %si, %di
+# CHECK-NEXT: 4.00 4.00 - - - - - - - - - - - - bsrw %si, %di
+# CHECK-NEXT: 4.00 4.00 - - - - - 1.00 - - - - - - bsfw (%rax), %di
+# CHECK-NEXT: 4.00 4.00 - - - - - 1.00 - - - - - - bsrw (%rax), %di
+# CHECK-NEXT: 4.00 4.00 - - - - - - - - - - - - bsfl %esi, %edi
+# CHECK-NEXT: 4.00 4.00 - - - - - - - - - - - - bsrl %esi, %edi
+# CHECK-NEXT: 4.00 4.00 - - - - - 1.00 - - - - - - bsfl (%rax), %edi
+# CHECK-NEXT: 4.00 4.00 - - - - - 1.00 - - - - - - bsrl (%rax), %edi
+# CHECK-NEXT: 4.00 4.00 - - - - - - - - - - - - bsfq %rsi, %rdi
+# CHECK-NEXT: 4.00 4.00 - - - - - - - - - - - - bsrq %rsi, %rdi
+# CHECK-NEXT: 4.00 4.00 - - - - - 1.00 - - - - - - bsfq (%rax), %rdi
+# CHECK-NEXT: 4.00 4.00 - - - - - 1.00 - - - - - - bsrq (%rax), %rdi
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - bswapl %eax
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - bswapq %rax
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - btw %si, %di
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