[PATCH] D46423: [WIP, RISCV] Support .option relax and .option norelax

[Lewis Revill via Phabricator via llvm-commits]

lewis-revill added a comment.

Just an update to my previous comment, I realised you were right @asb since we don't update the AsmBackend's SubtargetInfo anymore, so `getFeatureBits()[RISCV::FeatureRelax]` will still be true after parsing based on the `-mattr=relax`. I'm looking into potentially using only the `ForceRelocs` variable for relocation behaviour and trying to set this lazily when we parse an instruction that might be relaxed in a relaxable section to cover the case you mentioned. I'll update whether I think this is possible ASAP.


Repository:
  rL LLVM

https://reviews.llvm.org/D46423