[PATCH] D52293: [DagCombine][X86][AArch64] Try to unfold (X >> C1) & (C2 << C3) as ((X >> (C1 + C3)) & C2) << C3 (PR38938)

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri updated this revision to Diff 166603.
lebedev.ri retitled this revision from "[X86][BMI] BEXTR: handle  (X >> C1) & (C2 << C3)  as  ((X >> (C1 + C3)) & C2) << C3 (PR38938)" to "[DagCombine][X86][AArch64] Try to unfold  (X >> C1) & (C2 << C3)  as  ((X >> (C1 + C3)) & C2) << C3 (PR38938)".
lebedev.ri edited the summary of this revision.
lebedev.ri added a comment.
Herald added a reviewer: javed.absar.
Herald added a subscriber: kristof.beyls.

> Comment # 4 on bug 38938 from Craig Topper
> 
> We need to get the shl created before the address mode for the inc is
> selected
>  in Simon's test case. So we need to handle this in DAG combine or in
>  preprocessiseldag.

Ok, makes sense.
This turned out to be rather problematic :S

This is *very* prone to endless loops (we unfold the pattern,
and then `SimplifyDemandedBits` folds it back).
I suspect the change in `DAGCombiner::SimplifyDemandedBits()`
is **too** ugly, but i don't have any better ideas.
Anything else appears to deadlock.

These aren't all the test changes, but most of them.


Repository:
  rL LLVM

https://reviews.llvm.org/D52293

Files:
  include/llvm/CodeGen/TargetLowering.h
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  lib/Target/AArch64/AArch64ISelLowering.cpp
  lib/Target/AArch64/AArch64ISelLowering.h
  lib/Target/X86/X86ISelLowering.cpp
  lib/Target/X86/X86ISelLowering.h
  test/CodeGen/AArch64/expand-select.ll
  test/CodeGen/AArch64/selectcc-to-shiftand.ll
  test/CodeGen/AArch64/signbit-shift.ll
  test/CodeGen/X86/bmi-x86_64.ll
  test/CodeGen/X86/break-false-dep.ll
  test/CodeGen/X86/extract-bits.ll
  test/CodeGen/X86/selectcc-to-shiftand.ll

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