[PATCH] D38128: Handle COPYs of physregs better (regalloc hints)

[Sanjay Patel via Phabricator via llvm-commits]

spatel accepted this revision.
spatel added a comment.
This revision is now accepted and ready to land.

In https://reviews.llvm.org/D38128#1239512, @RKSimon wrote:

> In https://reviews.llvm.org/D38128#1239480, @niravd wrote:
>
> > I've gone through and marked all the places.
> >
> > > Is this just about the extra 'movdqa' in vector-shift-ashr-128.ll, or are there other diffs to look at?
>
>
> These are all due to pblendvb/blendvpd/blendvps being hardwired to use the xmm0 as the mask register (limit goes away for avx)


Yep - thanks for marking all of those. That corner case shouldn't hold up the general improvement, and the number of customers specifically targeting SSE4.1 should go to zero over time, so LGTM.


Repository:
  rL LLVM

https://reviews.llvm.org/D38128