[PATCH] D52174: [TableGen][SubtargetEmitter] Add the ability for processor models to describe dependency breaking instructions.

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon accepted this revision.
RKSimon added a comment.
This revision is now accepted and ready to land.

LGTM - the vandps/vandpd btver2 zero-idiom cases need cleaning up but have confirmed with @andreadb offline that he'll do this as a follow-up



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Comment at: lib/Target/X86/X86ScheduleBtVer2.td:716
+    VPXORrr, VPANDNrr, VXORPSrr, VXORPDrr,
+    VXORPSYrr, VXORPDYrr, VANDNPSrr, VANDNPDrr,
+    VPSUBBrr, VPSUBDrr, VPSUBQrr, VPSUBWrr,
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andreadb wrote:
> RKSimon wrote:
> > VANDNPSYrr/VANDNPDYrr?
> Interestingly, those were missing in the original implementation of `X86InstrAnalysis::isDependencyBreaking()`.
> 
> I have added them to the set.
> I have also added two extra tests for VANDNPSYrr/VANDNPDYrr in `test/tools/llvm-mca/BtVer2/zero-idioms-avx-256.s`
Possibly sort all these instructions so its easier to find a specific one?


https://reviews.llvm.org/D52174