[PATCH] D52174: [TableGen][SubtargetEmitter] Add the ability for processor models to describe dependency breaking instructions.

[Andrea Di Biagio via Phabricator via llvm-commits]

andreadb updated this revision to Diff 166100.
andreadb marked 3 inline comments as done.
andreadb added a comment.

Address review comments.

Also:

- Improved the description of class PredicateInfo.
- Removed two unused fields from tablegen class STIPredicate.
- Added extra verification checks to: a) explicitly disallow InstructionEquivalenceClass definitions with an empty set of opcodes; b) avoid that an instruction opcode is used by multiple equivalence classes of a same STIPredicate.


https://reviews.llvm.org/D52174

Files:
  include/llvm/CodeGen/TargetSubtargetInfo.h
  include/llvm/MC/MCInstrAnalysis.h
  include/llvm/Target/TargetInstrPredicate.td
  lib/MC/MCInstrAnalysis.cpp
  lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
  lib/Target/X86/X86ScheduleBtVer2.td
  test/tools/llvm-mca/X86/BtVer2/zero-idioms-avx-256.s
  tools/llvm-mca/lib/InstrBuilder.cpp
  utils/TableGen/CodeGenSchedule.cpp
  utils/TableGen/CodeGenSchedule.h
  utils/TableGen/PredicateExpander.cpp
  utils/TableGen/PredicateExpander.h
  utils/TableGen/SubtargetEmitter.cpp

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