[PATCH] D52123: [AMDGPU] Initialize instruction itinerary from GCNSubtarget

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL342400: [AMDGPU] Initialize instruction itinerary from GCNSubtarget (authored by rampitec, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D52123?vs=165594&id=165776#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D52123

Files:
  llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
  llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h


Index: llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
@@ -149,6 +149,7 @@
     TargetTriple(TT),
     Gen(SOUTHERN_ISLANDS),
     IsaVersion(ISAVersion0_0_0),
+    InstrItins(getInstrItineraryForCPU(GPU)),
     LDSBankCount(0),
     MaxPrivateElementSize(0),
 
Index: llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h
@@ -297,6 +297,7 @@
   Triple TargetTriple;
   unsigned Gen;
   unsigned IsaVersion;
+  InstrItineraryData InstrItins;
   int LDSBankCount;
   unsigned MaxPrivateElementSize;
 
@@ -420,6 +421,10 @@
     return &TSInfo;
   }
 
+  const InstrItineraryData *getInstrItineraryData() const override {
+    return &InstrItins;
+  }
+
   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
 
   Generation getGeneration() const {


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D52123.165776.patch
Type: text/x-patch
Size: 1090 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20180917/799b517a/attachment.bin>