[llvm] r342059 - [X86] Remove isel patterns for ADCX instruction
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 12 08:47:34 PDT 2018
Author: ctopper
Date: Wed Sep 12 08:47:34 2018
New Revision: 342059
URL: http://llvm.org/viewvc/llvm-project?rev=342059&view=rev
Log:
[X86] Remove isel patterns for ADCX instruction
There's no advantage to this instruction unless you need to avoid touching other flag bits. It's encoding is longer, it can't fold an immediate, it doesn't write all the flags.
I don't think gcc will generate this instruction either.
Fixes PR38852.
Differential Revision: https://reviews.llvm.org/D51754
Modified:
llvm/trunk/lib/Target/X86/X86InstrArithmetic.td
llvm/trunk/test/CodeGen/X86/adx-intrinsics-upgrade.ll
llvm/trunk/test/CodeGen/X86/adx-intrinsics.ll
llvm/trunk/test/CodeGen/X86/pr32282.ll
llvm/trunk/test/CodeGen/X86/pr32284.ll
llvm/trunk/test/CodeGen/X86/stack-folding-adx-x86_64.ll
Modified: llvm/trunk/lib/Target/X86/X86InstrArithmetic.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrArithmetic.td?rev=342059&r1=342058&r2=342059&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrArithmetic.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrArithmetic.td Wed Sep 12 08:47:34 2018
@@ -1307,22 +1307,18 @@ let Predicates = [HasBMI2] in {
//===----------------------------------------------------------------------===//
// ADCX and ADOX Instructions
//
+// We don't have patterns for these as there is no advantage over ADC for
+// most code.
let Predicates = [HasADX], Defs = [EFLAGS], Uses = [EFLAGS],
- Constraints = "$src1 = $dst", AddedComplexity = 10 in {
+ Constraints = "$src1 = $dst", hasSideEffects = 0 in {
let SchedRW = [WriteADC], isCommutable = 1 in {
def ADCX32rr : I<0xF6, MRMSrcReg, (outs GR32:$dst),
(ins GR32:$src1, GR32:$src2),
- "adcx{l}\t{$src2, $dst|$dst, $src2}",
- [(set GR32:$dst, EFLAGS,
- (X86adc_flag GR32:$src1, GR32:$src2, EFLAGS))]>, T8PD;
+ "adcx{l}\t{$src2, $dst|$dst, $src2}", []>, T8PD;
def ADCX64rr : RI<0xF6, MRMSrcReg, (outs GR64:$dst),
(ins GR64:$src1, GR64:$src2),
- "adcx{q}\t{$src2, $dst|$dst, $src2}",
- [(set GR64:$dst, EFLAGS,
- (X86adc_flag GR64:$src1, GR64:$src2, EFLAGS))]>, T8PD;
+ "adcx{q}\t{$src2, $dst|$dst, $src2}", []>, T8PD;
- // We don't have patterns for ADOX yet.
- let hasSideEffects = 0 in {
def ADOX32rr : I<0xF6, MRMSrcReg, (outs GR32:$dst),
(ins GR32:$src1, GR32:$src2),
"adox{l}\t{$src2, $dst|$dst, $src2}", []>, T8XS;
@@ -1330,26 +1326,17 @@ let Predicates = [HasADX], Defs = [EFLAG
def ADOX64rr : RI<0xF6, MRMSrcReg, (outs GR64:$dst),
(ins GR64:$src1, GR64:$src2),
"adox{q}\t{$src2, $dst|$dst, $src2}", []>, T8XS;
- } // hasSideEffects = 0
} // SchedRW
let mayLoad = 1, SchedRW = [WriteADCLd, ReadAfterLd] in {
def ADCX32rm : I<0xF6, MRMSrcMem, (outs GR32:$dst),
(ins GR32:$src1, i32mem:$src2),
- "adcx{l}\t{$src2, $dst|$dst, $src2}",
- [(set GR32:$dst, EFLAGS,
- (X86adc_flag GR32:$src1, (loadi32 addr:$src2), EFLAGS))]>,
- T8PD;
+ "adcx{l}\t{$src2, $dst|$dst, $src2}", []>, T8PD;
def ADCX64rm : RI<0xF6, MRMSrcMem, (outs GR64:$dst),
(ins GR64:$src1, i64mem:$src2),
- "adcx{q}\t{$src2, $dst|$dst, $src2}",
- [(set GR64:$dst, EFLAGS,
- (X86adc_flag GR64:$src1, (loadi64 addr:$src2), EFLAGS))]>,
- T8PD;
+ "adcx{q}\t{$src2, $dst|$dst, $src2}", []>, T8PD;
- // We don't have patterns for ADOX yet.
- let hasSideEffects = 0 in {
def ADOX32rm : I<0xF6, MRMSrcMem, (outs GR32:$dst),
(ins GR32:$src1, i32mem:$src2),
"adox{l}\t{$src2, $dst|$dst, $src2}", []>, T8XS;
@@ -1357,15 +1344,5 @@ let Predicates = [HasADX], Defs = [EFLAG
def ADOX64rm : RI<0xF6, MRMSrcMem, (outs GR64:$dst),
(ins GR64:$src1, i64mem:$src2),
"adox{q}\t{$src2, $dst|$dst, $src2}", []>, T8XS;
- } // hasSideEffects = 0
} // mayLoad = 1, SchedRW = [WriteADCLd]
}
-
-// Patterns to recognize loads on the LHS of an ADC. We can't make X86adc_flag
-// commutable since it has EFLAGs as an input.
-let Predicates = [HasADX], AddedComplexity = 10 in {
- def : Pat<(X86adc_flag (loadi32 addr:$src2), GR32:$src1, EFLAGS),
- (ADCX32rm GR32:$src1, addr:$src2)>;
- def : Pat<(X86adc_flag (loadi64 addr:$src2), GR64:$src1, EFLAGS),
- (ADCX64rm GR64:$src1, addr:$src2)>;
-}
Modified: llvm/trunk/test/CodeGen/X86/adx-intrinsics-upgrade.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/adx-intrinsics-upgrade.ll?rev=342059&r1=342058&r2=342059&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/adx-intrinsics-upgrade.ll (original)
+++ llvm/trunk/test/CodeGen/X86/adx-intrinsics-upgrade.ll Wed Sep 12 08:47:34 2018
@@ -5,21 +5,13 @@
declare i8 @llvm.x86.addcarryx.u32(i8, i32, i32, i8*)
define i8 @test_addcarryx_u32(i8 %c, i32 %a, i32 %b, i8* %ptr) {
-; NOADX-LABEL: test_addcarryx_u32:
-; NOADX: ## %bb.0:
-; NOADX-NEXT: addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
-; NOADX-NEXT: adcl %edx, %esi ## encoding: [0x11,0xd6]
-; NOADX-NEXT: setb %al ## encoding: [0x0f,0x92,0xc0]
-; NOADX-NEXT: movl %esi, (%rcx) ## encoding: [0x89,0x31]
-; NOADX-NEXT: retq ## encoding: [0xc3]
-;
-; ADX-LABEL: test_addcarryx_u32:
-; ADX: ## %bb.0:
-; ADX-NEXT: addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
-; ADX-NEXT: adcxl %edx, %esi ## encoding: [0x66,0x0f,0x38,0xf6,0xf2]
-; ADX-NEXT: setb %al ## encoding: [0x0f,0x92,0xc0]
-; ADX-NEXT: movl %esi, (%rcx) ## encoding: [0x89,0x31]
-; ADX-NEXT: retq ## encoding: [0xc3]
+; CHECK-LABEL: test_addcarryx_u32:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
+; CHECK-NEXT: adcl %edx, %esi ## encoding: [0x11,0xd6]
+; CHECK-NEXT: setb %al ## encoding: [0x0f,0x92,0xc0]
+; CHECK-NEXT: movl %esi, (%rcx) ## encoding: [0x89,0x31]
+; CHECK-NEXT: retq ## encoding: [0xc3]
%ret = tail call i8 @llvm.x86.addcarryx.u32(i8 %c, i32 %a, i32 %b, i8* %ptr)
ret i8 %ret;
}
@@ -27,21 +19,13 @@ define i8 @test_addcarryx_u32(i8 %c, i32
declare i8 @llvm.x86.addcarryx.u64(i8, i64, i64, i8*)
define i8 @test_addcarryx_u64(i8 %c, i64 %a, i64 %b, i8* %ptr) {
-; NOADX-LABEL: test_addcarryx_u64:
-; NOADX: ## %bb.0:
-; NOADX-NEXT: addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
-; NOADX-NEXT: adcq %rdx, %rsi ## encoding: [0x48,0x11,0xd6]
-; NOADX-NEXT: setb %al ## encoding: [0x0f,0x92,0xc0]
-; NOADX-NEXT: movq %rsi, (%rcx) ## encoding: [0x48,0x89,0x31]
-; NOADX-NEXT: retq ## encoding: [0xc3]
-;
-; ADX-LABEL: test_addcarryx_u64:
-; ADX: ## %bb.0:
-; ADX-NEXT: addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
-; ADX-NEXT: adcxq %rdx, %rsi ## encoding: [0x66,0x48,0x0f,0x38,0xf6,0xf2]
-; ADX-NEXT: setb %al ## encoding: [0x0f,0x92,0xc0]
-; ADX-NEXT: movq %rsi, (%rcx) ## encoding: [0x48,0x89,0x31]
-; ADX-NEXT: retq ## encoding: [0xc3]
+; CHECK-LABEL: test_addcarryx_u64:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
+; CHECK-NEXT: adcq %rdx, %rsi ## encoding: [0x48,0x11,0xd6]
+; CHECK-NEXT: setb %al ## encoding: [0x0f,0x92,0xc0]
+; CHECK-NEXT: movq %rsi, (%rcx) ## encoding: [0x48,0x89,0x31]
+; CHECK-NEXT: retq ## encoding: [0xc3]
%ret = tail call i8 @llvm.x86.addcarryx.u64(i8 %c, i64 %a, i64 %b, i8* %ptr)
ret i8 %ret;
}
@@ -49,21 +33,13 @@ define i8 @test_addcarryx_u64(i8 %c, i64
declare i8 @llvm.x86.addcarry.u32(i8, i32, i32, i8*)
define i8 @test_addcarry_u32(i8 %c, i32 %a, i32 %b, i8* %ptr) {
-; NOADX-LABEL: test_addcarry_u32:
-; NOADX: ## %bb.0:
-; NOADX-NEXT: addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
-; NOADX-NEXT: adcl %edx, %esi ## encoding: [0x11,0xd6]
-; NOADX-NEXT: setb %al ## encoding: [0x0f,0x92,0xc0]
-; NOADX-NEXT: movl %esi, (%rcx) ## encoding: [0x89,0x31]
-; NOADX-NEXT: retq ## encoding: [0xc3]
-;
-; ADX-LABEL: test_addcarry_u32:
-; ADX: ## %bb.0:
-; ADX-NEXT: addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
-; ADX-NEXT: adcxl %edx, %esi ## encoding: [0x66,0x0f,0x38,0xf6,0xf2]
-; ADX-NEXT: setb %al ## encoding: [0x0f,0x92,0xc0]
-; ADX-NEXT: movl %esi, (%rcx) ## encoding: [0x89,0x31]
-; ADX-NEXT: retq ## encoding: [0xc3]
+; CHECK-LABEL: test_addcarry_u32:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
+; CHECK-NEXT: adcl %edx, %esi ## encoding: [0x11,0xd6]
+; CHECK-NEXT: setb %al ## encoding: [0x0f,0x92,0xc0]
+; CHECK-NEXT: movl %esi, (%rcx) ## encoding: [0x89,0x31]
+; CHECK-NEXT: retq ## encoding: [0xc3]
%ret = tail call i8 @llvm.x86.addcarry.u32(i8 %c, i32 %a, i32 %b, i8* %ptr)
ret i8 %ret;
}
@@ -71,21 +47,13 @@ define i8 @test_addcarry_u32(i8 %c, i32
declare i8 @llvm.x86.addcarry.u64(i8, i64, i64, i8*)
define i8 @test_addcarry_u64(i8 %c, i64 %a, i64 %b, i8* %ptr) {
-; NOADX-LABEL: test_addcarry_u64:
-; NOADX: ## %bb.0:
-; NOADX-NEXT: addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
-; NOADX-NEXT: adcq %rdx, %rsi ## encoding: [0x48,0x11,0xd6]
-; NOADX-NEXT: setb %al ## encoding: [0x0f,0x92,0xc0]
-; NOADX-NEXT: movq %rsi, (%rcx) ## encoding: [0x48,0x89,0x31]
-; NOADX-NEXT: retq ## encoding: [0xc3]
-;
-; ADX-LABEL: test_addcarry_u64:
-; ADX: ## %bb.0:
-; ADX-NEXT: addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
-; ADX-NEXT: adcxq %rdx, %rsi ## encoding: [0x66,0x48,0x0f,0x38,0xf6,0xf2]
-; ADX-NEXT: setb %al ## encoding: [0x0f,0x92,0xc0]
-; ADX-NEXT: movq %rsi, (%rcx) ## encoding: [0x48,0x89,0x31]
-; ADX-NEXT: retq ## encoding: [0xc3]
+; CHECK-LABEL: test_addcarry_u64:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
+; CHECK-NEXT: adcq %rdx, %rsi ## encoding: [0x48,0x11,0xd6]
+; CHECK-NEXT: setb %al ## encoding: [0x0f,0x92,0xc0]
+; CHECK-NEXT: movq %rsi, (%rcx) ## encoding: [0x48,0x89,0x31]
+; CHECK-NEXT: retq ## encoding: [0xc3]
%ret = tail call i8 @llvm.x86.addcarry.u64(i8 %c, i64 %a, i64 %b, i8* %ptr)
ret i8 %ret;
}
@@ -120,27 +88,16 @@ define i8 @test_subborrow_u64(i8 %c, i64
; Try a version with loads. Previously we crashed on this.
define i32 @load_crash(i64* nocapture readonly %a, i64* nocapture readonly %b, i64* %res) {
-; NOADX-LABEL: load_crash:
-; NOADX: ## %bb.0:
-; NOADX-NEXT: movq (%rdi), %rax ## encoding: [0x48,0x8b,0x07]
-; NOADX-NEXT: xorl %ecx, %ecx ## encoding: [0x31,0xc9]
-; NOADX-NEXT: addb $-1, %cl ## encoding: [0x80,0xc1,0xff]
-; NOADX-NEXT: adcq (%rsi), %rax ## encoding: [0x48,0x13,0x06]
-; NOADX-NEXT: setb %cl ## encoding: [0x0f,0x92,0xc1]
-; NOADX-NEXT: movq %rax, (%rdx) ## encoding: [0x48,0x89,0x02]
-; NOADX-NEXT: movzbl %cl, %eax ## encoding: [0x0f,0xb6,0xc1]
-; NOADX-NEXT: retq ## encoding: [0xc3]
-;
-; ADX-LABEL: load_crash:
-; ADX: ## %bb.0:
-; ADX-NEXT: movq (%rdi), %rax ## encoding: [0x48,0x8b,0x07]
-; ADX-NEXT: xorl %ecx, %ecx ## encoding: [0x31,0xc9]
-; ADX-NEXT: addb $-1, %cl ## encoding: [0x80,0xc1,0xff]
-; ADX-NEXT: adcxq (%rsi), %rax ## encoding: [0x66,0x48,0x0f,0x38,0xf6,0x06]
-; ADX-NEXT: setb %cl ## encoding: [0x0f,0x92,0xc1]
-; ADX-NEXT: movq %rax, (%rdx) ## encoding: [0x48,0x89,0x02]
-; ADX-NEXT: movzbl %cl, %eax ## encoding: [0x0f,0xb6,0xc1]
-; ADX-NEXT: retq ## encoding: [0xc3]
+; CHECK-LABEL: load_crash:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: movq (%rdi), %rax ## encoding: [0x48,0x8b,0x07]
+; CHECK-NEXT: xorl %ecx, %ecx ## encoding: [0x31,0xc9]
+; CHECK-NEXT: addb $-1, %cl ## encoding: [0x80,0xc1,0xff]
+; CHECK-NEXT: adcq (%rsi), %rax ## encoding: [0x48,0x13,0x06]
+; CHECK-NEXT: setb %cl ## encoding: [0x0f,0x92,0xc1]
+; CHECK-NEXT: movq %rax, (%rdx) ## encoding: [0x48,0x89,0x02]
+; CHECK-NEXT: movzbl %cl, %eax ## encoding: [0x0f,0xb6,0xc1]
+; CHECK-NEXT: retq ## encoding: [0xc3]
%1 = load i64, i64* %a, align 8
%2 = load i64, i64* %b, align 8
%3 = bitcast i64* %res to i8*
Modified: llvm/trunk/test/CodeGen/X86/adx-intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/adx-intrinsics.ll?rev=342059&r1=342058&r2=342059&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/adx-intrinsics.ll (original)
+++ llvm/trunk/test/CodeGen/X86/adx-intrinsics.ll Wed Sep 12 08:47:34 2018
@@ -5,21 +5,13 @@
declare { i8, i32 } @llvm.x86.addcarryx.u32(i8, i32, i32)
define i8 @test_addcarryx_u32(i8 %c, i32 %a, i32 %b, i8* %ptr) {
-; NOADX-LABEL: test_addcarryx_u32:
-; NOADX: ## %bb.0:
-; NOADX-NEXT: addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
-; NOADX-NEXT: adcl %edx, %esi ## encoding: [0x11,0xd6]
-; NOADX-NEXT: setb %al ## encoding: [0x0f,0x92,0xc0]
-; NOADX-NEXT: movl %esi, (%rcx) ## encoding: [0x89,0x31]
-; NOADX-NEXT: retq ## encoding: [0xc3]
-;
-; ADX-LABEL: test_addcarryx_u32:
-; ADX: ## %bb.0:
-; ADX-NEXT: addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
-; ADX-NEXT: adcxl %edx, %esi ## encoding: [0x66,0x0f,0x38,0xf6,0xf2]
-; ADX-NEXT: setb %al ## encoding: [0x0f,0x92,0xc0]
-; ADX-NEXT: movl %esi, (%rcx) ## encoding: [0x89,0x31]
-; ADX-NEXT: retq ## encoding: [0xc3]
+; CHECK-LABEL: test_addcarryx_u32:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
+; CHECK-NEXT: adcl %edx, %esi ## encoding: [0x11,0xd6]
+; CHECK-NEXT: setb %al ## encoding: [0x0f,0x92,0xc0]
+; CHECK-NEXT: movl %esi, (%rcx) ## encoding: [0x89,0x31]
+; CHECK-NEXT: retq ## encoding: [0xc3]
%ret = call { i8, i32 } @llvm.x86.addcarryx.u32(i8 %c, i32 %a, i32 %b)
%1 = extractvalue { i8, i32 } %ret, 1
%2 = bitcast i8* %ptr to i32*
@@ -29,21 +21,13 @@ define i8 @test_addcarryx_u32(i8 %c, i32
}
define i8 @test_addcarryx_u32_load(i8 %c, i32* %aptr, i32 %b, i8* %ptr) {
-; NOADX-LABEL: test_addcarryx_u32_load:
-; NOADX: ## %bb.0:
-; NOADX-NEXT: addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
-; NOADX-NEXT: adcl (%rsi), %edx ## encoding: [0x13,0x16]
-; NOADX-NEXT: setb %al ## encoding: [0x0f,0x92,0xc0]
-; NOADX-NEXT: movl %edx, (%rcx) ## encoding: [0x89,0x11]
-; NOADX-NEXT: retq ## encoding: [0xc3]
-;
-; ADX-LABEL: test_addcarryx_u32_load:
-; ADX: ## %bb.0:
-; ADX-NEXT: addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
-; ADX-NEXT: adcxl (%rsi), %edx ## encoding: [0x66,0x0f,0x38,0xf6,0x16]
-; ADX-NEXT: setb %al ## encoding: [0x0f,0x92,0xc0]
-; ADX-NEXT: movl %edx, (%rcx) ## encoding: [0x89,0x11]
-; ADX-NEXT: retq ## encoding: [0xc3]
+; CHECK-LABEL: test_addcarryx_u32_load:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
+; CHECK-NEXT: adcl (%rsi), %edx ## encoding: [0x13,0x16]
+; CHECK-NEXT: setb %al ## encoding: [0x0f,0x92,0xc0]
+; CHECK-NEXT: movl %edx, (%rcx) ## encoding: [0x89,0x11]
+; CHECK-NEXT: retq ## encoding: [0xc3]
%a = load i32, i32* %aptr
%ret = call { i8, i32 } @llvm.x86.addcarryx.u32(i8 %c, i32 %a, i32 %b)
%1 = extractvalue { i8, i32 } %ret, 1
@@ -54,21 +38,13 @@ define i8 @test_addcarryx_u32_load(i8 %c
}
define i8 @test_addcarryx_u32_load2(i8 %c, i32 %a, i32* %bptr, i8* %ptr) {
-; NOADX-LABEL: test_addcarryx_u32_load2:
-; NOADX: ## %bb.0:
-; NOADX-NEXT: addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
-; NOADX-NEXT: adcl (%rdx), %esi ## encoding: [0x13,0x32]
-; NOADX-NEXT: setb %al ## encoding: [0x0f,0x92,0xc0]
-; NOADX-NEXT: movl %esi, (%rcx) ## encoding: [0x89,0x31]
-; NOADX-NEXT: retq ## encoding: [0xc3]
-;
-; ADX-LABEL: test_addcarryx_u32_load2:
-; ADX: ## %bb.0:
-; ADX-NEXT: addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
-; ADX-NEXT: adcxl (%rdx), %esi ## encoding: [0x66,0x0f,0x38,0xf6,0x32]
-; ADX-NEXT: setb %al ## encoding: [0x0f,0x92,0xc0]
-; ADX-NEXT: movl %esi, (%rcx) ## encoding: [0x89,0x31]
-; ADX-NEXT: retq ## encoding: [0xc3]
+; CHECK-LABEL: test_addcarryx_u32_load2:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
+; CHECK-NEXT: adcl (%rdx), %esi ## encoding: [0x13,0x32]
+; CHECK-NEXT: setb %al ## encoding: [0x0f,0x92,0xc0]
+; CHECK-NEXT: movl %esi, (%rcx) ## encoding: [0x89,0x31]
+; CHECK-NEXT: retq ## encoding: [0xc3]
%b = load i32, i32* %bptr
%ret = call { i8, i32 } @llvm.x86.addcarryx.u32(i8 %c, i32 %a, i32 %b)
%1 = extractvalue { i8, i32 } %ret, 1
@@ -81,21 +57,13 @@ define i8 @test_addcarryx_u32_load2(i8 %
declare { i8, i64 } @llvm.x86.addcarryx.u64(i8, i64, i64)
define i8 @test_addcarryx_u64(i8 %c, i64 %a, i64 %b, i8* %ptr) {
-; NOADX-LABEL: test_addcarryx_u64:
-; NOADX: ## %bb.0:
-; NOADX-NEXT: addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
-; NOADX-NEXT: adcq %rdx, %rsi ## encoding: [0x48,0x11,0xd6]
-; NOADX-NEXT: setb %al ## encoding: [0x0f,0x92,0xc0]
-; NOADX-NEXT: movq %rsi, (%rcx) ## encoding: [0x48,0x89,0x31]
-; NOADX-NEXT: retq ## encoding: [0xc3]
-;
-; ADX-LABEL: test_addcarryx_u64:
-; ADX: ## %bb.0:
-; ADX-NEXT: addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
-; ADX-NEXT: adcxq %rdx, %rsi ## encoding: [0x66,0x48,0x0f,0x38,0xf6,0xf2]
-; ADX-NEXT: setb %al ## encoding: [0x0f,0x92,0xc0]
-; ADX-NEXT: movq %rsi, (%rcx) ## encoding: [0x48,0x89,0x31]
-; ADX-NEXT: retq ## encoding: [0xc3]
+; CHECK-LABEL: test_addcarryx_u64:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
+; CHECK-NEXT: adcq %rdx, %rsi ## encoding: [0x48,0x11,0xd6]
+; CHECK-NEXT: setb %al ## encoding: [0x0f,0x92,0xc0]
+; CHECK-NEXT: movq %rsi, (%rcx) ## encoding: [0x48,0x89,0x31]
+; CHECK-NEXT: retq ## encoding: [0xc3]
%ret = call { i8, i64 } @llvm.x86.addcarryx.u64(i8 %c, i64 %a, i64 %b)
%1 = extractvalue { i8, i64 } %ret, 1
%2 = bitcast i8* %ptr to i64*
@@ -107,21 +75,13 @@ define i8 @test_addcarryx_u64(i8 %c, i64
declare { i8, i32 } @llvm.x86.addcarry.u32(i8, i32, i32)
define i8 @test_addcarry_u32(i8 %c, i32 %a, i32 %b, i8* %ptr) {
-; NOADX-LABEL: test_addcarry_u32:
-; NOADX: ## %bb.0:
-; NOADX-NEXT: addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
-; NOADX-NEXT: adcl %edx, %esi ## encoding: [0x11,0xd6]
-; NOADX-NEXT: setb %al ## encoding: [0x0f,0x92,0xc0]
-; NOADX-NEXT: movl %esi, (%rcx) ## encoding: [0x89,0x31]
-; NOADX-NEXT: retq ## encoding: [0xc3]
-;
-; ADX-LABEL: test_addcarry_u32:
-; ADX: ## %bb.0:
-; ADX-NEXT: addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
-; ADX-NEXT: adcxl %edx, %esi ## encoding: [0x66,0x0f,0x38,0xf6,0xf2]
-; ADX-NEXT: setb %al ## encoding: [0x0f,0x92,0xc0]
-; ADX-NEXT: movl %esi, (%rcx) ## encoding: [0x89,0x31]
-; ADX-NEXT: retq ## encoding: [0xc3]
+; CHECK-LABEL: test_addcarry_u32:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
+; CHECK-NEXT: adcl %edx, %esi ## encoding: [0x11,0xd6]
+; CHECK-NEXT: setb %al ## encoding: [0x0f,0x92,0xc0]
+; CHECK-NEXT: movl %esi, (%rcx) ## encoding: [0x89,0x31]
+; CHECK-NEXT: retq ## encoding: [0xc3]
%ret = call { i8, i32 } @llvm.x86.addcarry.u32(i8 %c, i32 %a, i32 %b)
%1 = extractvalue { i8, i32 } %ret, 1
%2 = bitcast i8* %ptr to i32*
@@ -133,21 +93,13 @@ define i8 @test_addcarry_u32(i8 %c, i32
declare { i8, i64 } @llvm.x86.addcarry.u64(i8, i64, i64)
define i8 @test_addcarry_u64(i8 %c, i64 %a, i64 %b, i8* %ptr) {
-; NOADX-LABEL: test_addcarry_u64:
-; NOADX: ## %bb.0:
-; NOADX-NEXT: addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
-; NOADX-NEXT: adcq %rdx, %rsi ## encoding: [0x48,0x11,0xd6]
-; NOADX-NEXT: setb %al ## encoding: [0x0f,0x92,0xc0]
-; NOADX-NEXT: movq %rsi, (%rcx) ## encoding: [0x48,0x89,0x31]
-; NOADX-NEXT: retq ## encoding: [0xc3]
-;
-; ADX-LABEL: test_addcarry_u64:
-; ADX: ## %bb.0:
-; ADX-NEXT: addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
-; ADX-NEXT: adcxq %rdx, %rsi ## encoding: [0x66,0x48,0x0f,0x38,0xf6,0xf2]
-; ADX-NEXT: setb %al ## encoding: [0x0f,0x92,0xc0]
-; ADX-NEXT: movq %rsi, (%rcx) ## encoding: [0x48,0x89,0x31]
-; ADX-NEXT: retq ## encoding: [0xc3]
+; CHECK-LABEL: test_addcarry_u64:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
+; CHECK-NEXT: adcq %rdx, %rsi ## encoding: [0x48,0x11,0xd6]
+; CHECK-NEXT: setb %al ## encoding: [0x0f,0x92,0xc0]
+; CHECK-NEXT: movq %rsi, (%rcx) ## encoding: [0x48,0x89,0x31]
+; CHECK-NEXT: retq ## encoding: [0xc3]
%ret = call { i8, i64 } @llvm.x86.addcarry.u64(i8 %c, i64 %a, i64 %b)
%1 = extractvalue { i8, i64 } %ret, 1
%2 = bitcast i8* %ptr to i64*
@@ -194,27 +146,16 @@ define i8 @test_subborrow_u64(i8 %c, i64
; Try a version with loads. Previously we crashed on this.
define i32 @load_crash(i64* nocapture readonly %a, i64* nocapture readonly %b, i64* %res) {
-; NOADX-LABEL: load_crash:
-; NOADX: ## %bb.0:
-; NOADX-NEXT: movq (%rdi), %rax ## encoding: [0x48,0x8b,0x07]
-; NOADX-NEXT: xorl %ecx, %ecx ## encoding: [0x31,0xc9]
-; NOADX-NEXT: addb $-1, %cl ## encoding: [0x80,0xc1,0xff]
-; NOADX-NEXT: adcq (%rsi), %rax ## encoding: [0x48,0x13,0x06]
-; NOADX-NEXT: setb %cl ## encoding: [0x0f,0x92,0xc1]
-; NOADX-NEXT: movq %rax, (%rdx) ## encoding: [0x48,0x89,0x02]
-; NOADX-NEXT: movzbl %cl, %eax ## encoding: [0x0f,0xb6,0xc1]
-; NOADX-NEXT: retq ## encoding: [0xc3]
-;
-; ADX-LABEL: load_crash:
-; ADX: ## %bb.0:
-; ADX-NEXT: movq (%rdi), %rax ## encoding: [0x48,0x8b,0x07]
-; ADX-NEXT: xorl %ecx, %ecx ## encoding: [0x31,0xc9]
-; ADX-NEXT: addb $-1, %cl ## encoding: [0x80,0xc1,0xff]
-; ADX-NEXT: adcxq (%rsi), %rax ## encoding: [0x66,0x48,0x0f,0x38,0xf6,0x06]
-; ADX-NEXT: setb %cl ## encoding: [0x0f,0x92,0xc1]
-; ADX-NEXT: movq %rax, (%rdx) ## encoding: [0x48,0x89,0x02]
-; ADX-NEXT: movzbl %cl, %eax ## encoding: [0x0f,0xb6,0xc1]
-; ADX-NEXT: retq ## encoding: [0xc3]
+; CHECK-LABEL: load_crash:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: movq (%rdi), %rax ## encoding: [0x48,0x8b,0x07]
+; CHECK-NEXT: xorl %ecx, %ecx ## encoding: [0x31,0xc9]
+; CHECK-NEXT: addb $-1, %cl ## encoding: [0x80,0xc1,0xff]
+; CHECK-NEXT: adcq (%rsi), %rax ## encoding: [0x48,0x13,0x06]
+; CHECK-NEXT: setb %cl ## encoding: [0x0f,0x92,0xc1]
+; CHECK-NEXT: movq %rax, (%rdx) ## encoding: [0x48,0x89,0x02]
+; CHECK-NEXT: movzbl %cl, %eax ## encoding: [0x0f,0xb6,0xc1]
+; CHECK-NEXT: retq ## encoding: [0xc3]
%1 = load i64, i64* %a, align 8
%2 = load i64, i64* %b, align 8
%3 = bitcast i64* %res to i8*
Modified: llvm/trunk/test/CodeGen/X86/pr32282.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr32282.ll?rev=342059&r1=342058&r2=342059&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr32282.ll (original)
+++ llvm/trunk/test/CodeGen/X86/pr32282.ll Wed Sep 12 08:47:34 2018
@@ -23,10 +23,9 @@ define void @foo() {
; X86-NEXT: shrdl $21, %ecx, %eax
; X86-NEXT: shrl $21, %ecx
; X86-NEXT: andl $-2, %eax
-; X86-NEXT: xorl %edx, %edx
; X86-NEXT: addl $7, %eax
-; X86-NEXT: adcxl %ecx, %edx
-; X86-NEXT: pushl %edx
+; X86-NEXT: adcl $0, %ecx
+; X86-NEXT: pushl %ecx
; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl %eax
; X86-NEXT: .cfi_adjust_cfa_offset 4
Modified: llvm/trunk/test/CodeGen/X86/pr32284.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr32284.ll?rev=342059&r1=342058&r2=342059&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr32284.ll (original)
+++ llvm/trunk/test/CodeGen/X86/pr32284.ll Wed Sep 12 08:47:34 2018
@@ -207,9 +207,8 @@ define void @f1() {
; 686-O0-NEXT: subl $-1, %esi
; 686-O0-NEXT: sete %bl
; 686-O0-NEXT: movzbl %bl, %edi
-; 686-O0-NEXT: xorl %ebp, %ebp
; 686-O0-NEXT: addl $7093, %ecx # imm = 0x1BB5
-; 686-O0-NEXT: adcxl %ebp, %edx
+; 686-O0-NEXT: adcl $0, %edx
; 686-O0-NEXT: subl %edi, %ecx
; 686-O0-NEXT: sbbl $0, %edx
; 686-O0-NEXT: setl %bl
@@ -223,8 +222,8 @@ define void @f1() {
; 686-O0-NEXT: movl %ebp, _ZN8struct_210member_2_0E
; 686-O0-NEXT: movl $0, _ZN8struct_210member_2_0E+4
; 686-O0-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; 686-O0-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; 686-O0-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; 686-O0-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; 686-O0-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; 686-O0-NEXT: movl %edi, (%esp) # 4-byte Spill
; 686-O0-NEXT: addl $24, %esp
@@ -241,14 +240,11 @@ define void @f1() {
;
; 686-LABEL: f1:
; 686: # %bb.0: # %entry
-; 686-NEXT: pushl %edi
-; 686-NEXT: .cfi_def_cfa_offset 8
; 686-NEXT: pushl %esi
-; 686-NEXT: .cfi_def_cfa_offset 12
+; 686-NEXT: .cfi_def_cfa_offset 8
; 686-NEXT: subl $1, %esp
-; 686-NEXT: .cfi_def_cfa_offset 13
-; 686-NEXT: .cfi_offset %esi, -12
-; 686-NEXT: .cfi_offset %edi, -8
+; 686-NEXT: .cfi_def_cfa_offset 9
+; 686-NEXT: .cfi_offset %esi, -8
; 686-NEXT: movl var_5, %edx
; 686-NEXT: movl %edx, %eax
; 686-NEXT: xorl $208307499, %eax # imm = 0xC6A852B
@@ -266,11 +262,10 @@ define void @f1() {
; 686-NEXT: xorl %ecx, %ecx
; 686-NEXT: cmpl $-1, %edx
; 686-NEXT: sete %cl
-; 686-NEXT: xorl %edi, %edi
; 686-NEXT: addl $7093, %edx # imm = 0x1BB5
-; 686-NEXT: adcxl %esi, %edi
+; 686-NEXT: adcl $0, %esi
; 686-NEXT: cmpl %ecx, %edx
-; 686-NEXT: sbbl $0, %edi
+; 686-NEXT: sbbl $0, %esi
; 686-NEXT: setl %cl
; 686-NEXT: movzbl %cl, %ecx
; 686-NEXT: movl %ecx, var_57
@@ -278,10 +273,8 @@ define void @f1() {
; 686-NEXT: movl %eax, _ZN8struct_210member_2_0E
; 686-NEXT: movl $0, _ZN8struct_210member_2_0E+4
; 686-NEXT: addl $1, %esp
-; 686-NEXT: .cfi_def_cfa_offset 12
-; 686-NEXT: popl %esi
; 686-NEXT: .cfi_def_cfa_offset 8
-; 686-NEXT: popl %edi
+; 686-NEXT: popl %esi
; 686-NEXT: .cfi_def_cfa_offset 4
; 686-NEXT: retl
entry:
Modified: llvm/trunk/test/CodeGen/X86/stack-folding-adx-x86_64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/stack-folding-adx-x86_64.ll?rev=342059&r1=342058&r2=342059&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/stack-folding-adx-x86_64.ll (original)
+++ llvm/trunk/test/CodeGen/X86/stack-folding-adx-x86_64.ll Wed Sep 12 08:47:34 2018
@@ -1,4 +1,5 @@
-; RUN: llc -O3 -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+adx < %s | FileCheck %s
+; RUN: llc -O3 -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+adx < %s | FileCheck %s --check-prefix=CHECK --check-prefix=ADX
+; RUN: llc -O3 -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=-adx < %s | FileCheck %s --check-prefix=CHECK --check-prefix=NOADX
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-unknown"
@@ -10,7 +11,7 @@ target triple = "x86_64-unknown-unknown"
define i8 @stack_fold_addcarry_u32(i8 %a0, i32 %a1, i32 %a2, i8* %a3) {
;CHECK-LABEL: stack_fold_addcarry_u32
- ;CHECK: adcxl {{-?[0-9]*}}(%rsp), %{{.*}} {{.*#+}} 4-byte Folded Reload
+ ;CHECK: adcl {{-?[0-9]*}}(%rsp), %{{.*}} {{.*#+}} 4-byte Folded Reload
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
%2 = tail call i8 @llvm.x86.addcarry.u32(i8 %a0, i32 %a1, i32 %a2, i8* %a3)
ret i8 %2;
@@ -19,7 +20,7 @@ declare i8 @llvm.x86.addcarry.u32(i8, i3
define i8 @stack_fold_addcarry_u64(i8 %a0, i64 %a1, i64 %a2, i8* %a3) {
;CHECK-LABEL: stack_fold_addcarry_u64
- ;CHECK: adcxq {{-?[0-9]*}}(%rsp), %{{.*}} {{.*#+}} 8-byte Folded Reload
+ ;CHECK: adcq {{-?[0-9]*}}(%rsp), %{{.*}} {{.*#+}} 8-byte Folded Reload
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
%2 = tail call i8 @llvm.x86.addcarry.u64(i8 %a0, i64 %a1, i64 %a2, i8* %a3)
ret i8 %2;
@@ -28,7 +29,7 @@ declare i8 @llvm.x86.addcarry.u64(i8, i6
define i8 @stack_fold_addcarryx_u32(i8 %a0, i32 %a1, i32 %a2, i8* %a3) {
;CHECK-LABEL: stack_fold_addcarryx_u32
- ;CHECK: adcxl {{-?[0-9]*}}(%rsp), %{{.*}} {{.*#+}} 4-byte Folded Reload
+ ;CHECK: adcl {{-?[0-9]*}}(%rsp), %{{.*}} {{.*#+}} 4-byte Folded Reload
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
%2 = tail call i8 @llvm.x86.addcarryx.u32(i8 %a0, i32 %a1, i32 %a2, i8* %a3)
ret i8 %2;
@@ -37,7 +38,7 @@ declare i8 @llvm.x86.addcarryx.u32(i8, i
define i8 @stack_fold_addcarryx_u64(i8 %a0, i64 %a1, i64 %a2, i8* %a3) {
;CHECK-LABEL: stack_fold_addcarryx_u64
- ;CHECK: adcxq {{-?[0-9]*}}(%rsp), %{{.*}} {{.*#+}} 8-byte Folded Reload
+ ;CHECK: adcq {{-?[0-9]*}}(%rsp), %{{.*}} {{.*#+}} 8-byte Folded Reload
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
%2 = tail call i8 @llvm.x86.addcarryx.u64(i8 %a0, i64 %a1, i64 %a2, i8* %a3)
ret i8 %2;
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