[llvm] r341658 - Add support for getRegisterByName.

[Sid Manning via llvm-commits]

Author: sidneym
Date: Fri Sep  7 06:36:21 2018
New Revision: 341658

URL: http://llvm.org/viewvc/llvm-project?rev=341658&view=rev
Log:
Add support for getRegisterByName.

Support required to build the Hexagon Linux kernel.

Differential Revision: https://reviews.llvm.org/D51363

Added:
    llvm/trunk/test/CodeGen/Hexagon/namedreg.ll
Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
    llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h

Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp?rev=341658&r1=341657&r2=341658&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp Fri Sep  7 06:36:21 2018
@@ -22,6 +22,7 @@
 #include "llvm/ADT/APInt.h"
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/StringSwitch.h"
 #include "llvm/CodeGen/CallingConvLower.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
@@ -240,6 +241,18 @@ bool HexagonTargetLowering::mayBeEmitted
   return true;
 }
 
+unsigned  HexagonTargetLowering::getRegisterByName(const char* RegName, EVT VT,
+                                              SelectionDAG &DAG) const {
+  // Just support r19, the linux kernel uses it.
+  unsigned Reg = StringSwitch<unsigned>(RegName)
+                     .Case("r19", Hexagon::R19)
+                     .Default(0);
+  if (Reg)
+    return Reg;
+
+  report_fatal_error("Invalid register name global variable");
+}
+
 /// LowerCallResult - Lower the result values of an ISD::CALL into the
 /// appropriate copies out of appropriate physical registers.  This assumes that
 /// Chain/Glue are the input chain/glue to use, and that TheCall is the call

Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h?rev=341658&r1=341657&r2=341658&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h Fri Sep  7 06:36:21 2018
@@ -223,6 +223,9 @@ namespace HexagonISD {
 
     bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
 
+    unsigned getRegisterByName(const char* RegName, EVT VT,
+                               SelectionDAG &DAG) const override;
+
     /// If a physical register, this returns the register that receives the
     /// exception address on entry to an EH pad.
     unsigned

Added: llvm/trunk/test/CodeGen/Hexagon/namedreg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/namedreg.ll?rev=341658&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/namedreg.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/namedreg.ll Fri Sep  7 06:36:21 2018
@@ -0,0 +1,13 @@
+; RUN: llc -mattr=+reserved-r19 -march=hexagon < %s | FileCheck %s
+define dso_local i32 @r19f() #0 {
+entry:
+  %0 = call i32 @llvm.read_register.i32(metadata !0)
+  ret i32 %0
+}
+
+declare i32 @llvm.read_register.i32(metadata) #1
+
+!llvm.named.register.r19 = !{!0}
+
+!0 = !{!"r19"}
+; CHECK: r0 = r19