[PATCH] D51726: [AMDGPU] Remove non-instructions from GCNHazardRecognizer buffer

[Carl Ritson via Phabricator via llvm-commits]

critson created this revision.
critson added reviewers: nhaehnle, arsenm.
Herald added subscribers: llvm-commits, t-tye, tpr, dstuttard, yaxunl, wdng, jvesely, kzhuravl.

This fixes a bug where a large number of implicit def instructions can cause the GCNHazardRecognizer not to insert required NOPs.

Change-Id: Ie75338f94de704ee5816b05afd0c922c6748a95b


Repository:
  rL LLVM

https://reviews.llvm.org/D51726

Files:
  lib/Target/AMDGPU/GCNHazardRecognizer.cpp
  test/CodeGen/AMDGPU/hazard-lookahead.mir


Index: test/CodeGen/AMDGPU/hazard-lookahead.mir
===================================================================
--- /dev/null
+++ test/CodeGen/AMDGPU/hazard-lookahead.mir
@@ -0,0 +1,46 @@
+# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass  post-RA-hazard-rec %s -o - | FileCheck --check-prefixes=GCN,GFX89 %s
+# RUN: llc -march=amdgcn -mcpu=gfx803 -verify-machineinstrs -run-pass  post-RA-hazard-rec %s -o - | FileCheck --check-prefixes=GCN,GFX89 %s
+
+# IMPLICIT_DEF/DBG_VALUE instructions should not prevent the hazard recognizer
+# from adding s_nop instructions between m0 update and s_sendmsg.
+
+---
+name: hazard-lookahead-implicit-def
+body: |
+  ; GCN-LABEL: name: hazard-lookahead-implicit-def
+  ; GCN: $vgpr6 = IMPLICIT_DEF
+  ; GFX89: S_NOP 0
+  ; GCN: S_SENDMSG 3, implicit $exec, implicit $m0
+
+  bb.0:
+    $m0 = S_MOV_B32 killed $sgpr12
+    $vgpr0 = IMPLICIT_DEF
+    $vgpr1 = IMPLICIT_DEF
+    $vgpr2 = IMPLICIT_DEF
+    $vgpr3 = IMPLICIT_DEF
+    $vgpr4 = IMPLICIT_DEF
+    $vgpr5 = IMPLICIT_DEF
+    $vgpr6 = IMPLICIT_DEF
+    S_SENDMSG 3, implicit $exec, implicit $m0
+    S_ENDPGM
+...
+---
+name: hazard-lookahead-dbg-value
+body: |
+  ; GCN-LABEL: name: hazard-lookahead-dbg-value
+  ; GCN: DBG_VALUE 6
+  ; GFX89: S_NOP 0
+  ; GCN: S_SENDMSG 3, implicit $exec, implicit $m0
+
+  bb.0:
+    $m0 = S_MOV_B32 killed $sgpr12
+    DBG_VALUE 0
+    DBG_VALUE 1
+    DBG_VALUE 2
+    DBG_VALUE 3
+    DBG_VALUE 4
+    DBG_VALUE 5
+    DBG_VALUE 6
+    S_SENDMSG 3, implicit $exec, implicit $m0
+    S_ENDPGM
+...
Index: lib/Target/AMDGPU/GCNHazardRecognizer.cpp
===================================================================
--- lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+++ lib/Target/AMDGPU/GCNHazardRecognizer.cpp
@@ -215,6 +215,13 @@
   if (!CurrCycleInstr)
     return;
 
+  // Do not track non-instructions which do not affect the wait states.
+  // If included, these instructions can lead to buffer overflow such that
+  // detectable hazards are missed.
+  unsigned Opcode = CurrCycleInstr->getOpcode();
+  if (Opcode == AMDGPU::DBG_VALUE || Opcode == AMDGPU::IMPLICIT_DEF)
+    return;
+
   unsigned NumWaitStates = TII.getNumWaitStates(*CurrCycleInstr);
 
   // Keep track of emitted instructions
@@ -253,8 +260,7 @@
         return WaitStates;
 
       unsigned Opcode = MI->getOpcode();
-      if (Opcode == AMDGPU::DBG_VALUE || Opcode == AMDGPU::IMPLICIT_DEF ||
-          Opcode == AMDGPU::INLINEASM)
+      if (Opcode == AMDGPU::INLINEASM)
         continue;
     }
     ++WaitStates;


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