[PATCH] D51706: ARM64: improve non-zero memset isel by ~2x

[JF Bastien via Phabricator via llvm-commits]

jfb created this revision.
jfb added reviewers: t.p.northover, MatzeB.
Herald added a reviewer: javed.absar.
Herald added subscribers: llvm-commits, dexonsmith, chrib, kristof.beyls, eraman.

I added a few ARM64 memset codegen tests in r341406 and r341493, and annotated
where the generated code was bad. This patch fixes the majority of the issues by
requesting that a 2xi64 vector be used for memset of 32 bytes and above.

The patch leaves the former request for f128 unchanged, despite f128
materialization being suboptimal: doing otherwise runs into other asserts in
isel and makes this patch too broad.

This patch hides the issue that was present in bzero_40_stack and bzero_72_stack
because the code now generates in a better order which doesn't have the store
offset issue. I'm not aware of that issue appearing elsewhere at the moment.

rdar://problem/44157755


Repository:
  rL LLVM

https://reviews.llvm.org/D51706

Files:
  lib/Target/AArch64/AArch64ISelLowering.cpp
  test/CodeGen/AArch64/arm64-memset-inline.ll

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