[PATCH] D48580: [AArch64] Support reserving x1-7 registers.

[Tri Vo via Phabricator via llvm-commits]

trong marked an inline comment as done.
trong added inline comments.


================
Comment at: lib/Target/AArch64/AArch64RegisterInfo.cpp:173
+                                          AArch64::X6, AArch64::X7 };
+  return std::any_of(std::begin(GPRArgRegs), std::end(GPRArgRegs),
+                     [this, &MF](MCPhysReg r){return isReservedReg(MF, r);});
----------------
nickdesaulniers wrote:
> consider using const iterators (`cbegin`, `cend`) if you're not modifying the iterated value.
`cbegin` and `cend` are c++14 which isn't required to build llvm/clang 


================
Comment at: lib/Target/AArch64/AArch64Subtarget.h:230
+  bool isXRegisterReserved(size_t i) const { return ReserveXRegister[i]; }
+  bool getNumXRegisterReserved() const { return ReserveXRegister.count(); }
   bool hasFPARMv8() const { return HasFPARMv8; }
----------------
nickdesaulniers wrote:
> return type `bool`?
oops


https://reviews.llvm.org/D48580