[PATCH] D51478: [AArch64] NFC: Refactoring to prepare for vector PCS.

[Francis Visoiu Mistrih via Phabricator via llvm-commits]

thegameg added inline comments.


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Comment at: lib/Target/AArch64/AArch64FrameLowering.cpp:495
   }
 
   (void)Opc;
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You can probably get rid of this now.


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Comment at: lib/Target/AArch64/AArch64FrameLowering.cpp:1377
+       LdrOpc = RPI.isPaired() ? AArch64::LDPXi : AArch64::LDRXui;
+       Size = RPI.isPaired() ? 16 : 8;
+       Align = 8;
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I think the size should always be 8 even if it's paired. The instruction will end up having 2 x MachineMemOperand load of size 8.


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Comment at: test/CodeGen/AArch64/unfold-masked-merge-scalar-constmask-innerouter.ll:209
 ; CHECK-NEXT:    mov w0, w20
-; CHECK-NEXT:    stp x19, x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-NEXT:    stp x19, x30, [sp, #16] // 16-byte Folded Spill
 ; CHECK-NEXT:    mov w19, w1
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I agree that this should be fixed, but I think the assumption [[ https://github.com/llvm-mirror/llvm/blob/3d765ce4b7f2fd25bdbc0efc26afdf42e84fecb2/lib/CodeGen/AsmPrinter/AsmPrinter.cpp#L752 | here ]] is wrong, and I think this is where this should be fixed.


https://reviews.llvm.org/D51478