[PATCH] D51474: Consider CSRs in computeRegisterLiveness

Matt Arsenault via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Aug 29 23:12:05 PDT 2018


arsenm created this revision.
arsenm added a reviewer: MatzeB.
Herald added subscribers: kristof.beyls, tpr, wdng.
Herald added a reviewer: javed.absar.

I'm not sure how to test this. The AMDGPU use
case registers aren't CSRs.

      

ARM is the only other user, and mostly uses it for
CPSR which also isn't a CSR.

      

The use in getImplicitSPRUseForDPRUse seems like
it may be possible to use a CSR here, but so far
I don't know enough about ARM to come up with an
example where this matters.


https://reviews.llvm.org/D51474

Files:
  lib/CodeGen/MachineBasicBlock.cpp


Index: lib/CodeGen/MachineBasicBlock.cpp
===================================================================
--- lib/CodeGen/MachineBasicBlock.cpp
+++ lib/CodeGen/MachineBasicBlock.cpp
@@ -16,6 +16,7 @@
 #include "llvm/CodeGen/LiveIntervals.h"
 #include "llvm/CodeGen/LiveVariables.h"
 #include "llvm/CodeGen/MachineDominators.h"
+#include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineLoopInfo.h"
@@ -1400,6 +1401,23 @@
   // If we reached the end, it is safe to clobber Reg at the end of a block of
   // no successor has it live in.
   if (I == end()) {
+    if (isReturnBlock()) {
+      const MachineFunction &MF = *getParent();
+      const MachineRegisterInfo &MRI = MF.getRegInfo();
+      for (const MCPhysReg *CSR = MRI.getCalleeSavedRegs(); CSR && *CSR; ++CSR) {
+        if (*CSR == Reg)
+          return LQR_Live;
+      }
+
+      const MachineFrameInfo &MFI = MF.getFrameInfo();
+      if (MFI.isCalleeSavedInfoValid()) {
+        for (const CalleeSavedInfo &Info : MFI.getCalleeSavedInfo()) {
+          if (Info.isRestored() && Info.getReg() == Reg)
+            return LQR_Live;
+        }
+      }
+    }
+
     for (MachineBasicBlock *S : successors()) {
       for (MCSubRegIterator SubReg(Reg, TRI, /*IncludeSelf*/true);
            SubReg.isValid(); ++SubReg) {


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