[llvm] r341022 - [X86] Make Feature64Bit useful
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 29 23:01:05 PDT 2018
Author: ctopper
Date: Wed Aug 29 23:01:05 2018
New Revision: 341022
URL: http://llvm.org/viewvc/llvm-project?rev=341022&view=rev
Log:
[X86] Make Feature64Bit useful
We now only add +64bit to the CPU string for "generic" CPU. All other CPU names are assumed to have the feature flag already set if they support 64-bit. I've remove the implies from CMPXCHG8 so that Feature64Bit only comes in via CPUs or user passing -mattr=+64bit.
I've changed the assert to a report_fatal_error so it's not lost in Release builds.
The test updates are to fix things that tripped the new error.
Differential Revision: https://reviews.llvm.org/D51231
Modified:
llvm/trunk/lib/Target/X86/X86.td
llvm/trunk/lib/Target/X86/X86Subtarget.cpp
llvm/trunk/test/CodeGen/X86/cpus.ll
llvm/trunk/test/CodeGen/X86/early-ifcvt-crash.ll
llvm/trunk/test/CodeGen/X86/pr11985.ll
llvm/trunk/test/CodeGen/X86/pr34080.ll
llvm/trunk/test/CodeGen/X86/x86-64-double-shifts-var.ll
llvm/trunk/test/ThinLTO/X86/cache-config.ll
llvm/trunk/test/Transforms/LoopUnroll/X86/partial.ll
Modified: llvm/trunk/lib/Target/X86/X86.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=341022&r1=341021&r2=341022&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86.td (original)
+++ llvm/trunk/lib/Target/X86/X86.td Wed Aug 29 23:01:05 2018
@@ -88,12 +88,12 @@ def Feature3DNowA : SubtargetFeature<"3
[Feature3DNow]>;
// All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
// feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
-// without disabling 64-bit mode.
+// without disabling 64-bit mode. Nothing should imply this feature bit. It
+// is used to enforce that only 64-bit capable CPUs are used in 64-bit mode.
def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true",
"Support 64-bit instructions">;
def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true",
- "64-bit with cmpxchg16b",
- [Feature64Bit]>;
+ "64-bit with cmpxchg16b">;
def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
"SHLD instruction is slow">;
def FeatureSlowPMULLD : SubtargetFeature<"slow-pmulld", "IsPMULLDSlow", "true",
@@ -520,6 +520,7 @@ def : ProcessorModel<"nocona", GenericPo
FeatureSSE3,
FeatureFXSR,
FeatureNOPL,
+ Feature64Bit,
FeatureCMPXCHG16B
]>;
@@ -532,6 +533,7 @@ def : ProcessorModel<"core2", SandyBridg
FeatureSSSE3,
FeatureFXSR,
FeatureNOPL,
+ Feature64Bit,
FeatureCMPXCHG16B,
FeatureLAHFSAHF,
FeatureMacroFusion
@@ -544,6 +546,7 @@ def : ProcessorModel<"penryn", SandyBrid
FeatureSSE41,
FeatureFXSR,
FeatureNOPL,
+ Feature64Bit,
FeatureCMPXCHG16B,
FeatureLAHFSAHF,
FeatureMacroFusion
@@ -559,6 +562,7 @@ class BonnellProc<string Name> : Process
FeatureSSSE3,
FeatureFXSR,
FeatureNOPL,
+ Feature64Bit,
FeatureCMPXCHG16B,
FeatureMOVBE,
FeatureLEAForSP,
@@ -580,6 +584,7 @@ class SilvermontProc<string Name> : Proc
FeatureSSE42,
FeatureFXSR,
FeatureNOPL,
+ Feature64Bit,
FeatureCMPXCHG16B,
FeatureMOVBE,
FeaturePOPCNT,
@@ -615,6 +620,7 @@ def GLMFeatures : ProcessorFeatures<[],
FeatureSSE42,
FeatureFXSR,
FeatureNOPL,
+ Feature64Bit,
FeatureCMPXCHG16B,
FeatureMOVBE,
FeaturePOPCNT,
@@ -675,6 +681,7 @@ class NehalemProc<string Name> : Process
FeatureSSE42,
FeatureFXSR,
FeatureNOPL,
+ Feature64Bit,
FeatureCMPXCHG16B,
FeaturePOPCNT,
FeatureLAHFSAHF,
@@ -692,6 +699,7 @@ class WestmereProc<string Name> : Proces
FeatureSSE42,
FeatureFXSR,
FeatureNOPL,
+ Feature64Bit,
FeatureCMPXCHG16B,
FeaturePOPCNT,
FeatureAES,
@@ -710,6 +718,7 @@ def SNBFeatures : ProcessorFeatures<[],
FeatureAVX,
FeatureFXSR,
FeatureNOPL,
+ Feature64Bit,
FeatureCMPXCHG16B,
FeaturePOPCNT,
FeatureAES,
@@ -927,13 +936,13 @@ foreach P = ["k8", "opteron", "athlon64"
foreach P = ["k8-sse3", "opteron-sse3", "athlon64-sse3"] in {
def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureSSE3, Feature3DNowA,
FeatureFXSR, FeatureNOPL, FeatureCMPXCHG16B, FeatureSlowSHLD,
- FeatureCMOV]>;
+ FeatureCMOV, Feature64Bit]>;
}
foreach P = ["amdfam10", "barcelona"] in {
def : Proc<P, [FeatureX87, FeatureSSE4A, Feature3DNowA, FeatureFXSR,
FeatureNOPL, FeatureCMPXCHG16B, FeatureLZCNT, FeaturePOPCNT,
- FeatureSlowSHLD, FeatureLAHFSAHF, FeatureCMOV]>;
+ FeatureSlowSHLD, FeatureLAHFSAHF, FeatureCMOV, Feature64Bit]>;
}
// Bobcat
@@ -945,6 +954,7 @@ def : Proc<"btver1", [
FeatureSSE4A,
FeatureFXSR,
FeatureNOPL,
+ Feature64Bit,
FeatureCMPXCHG16B,
FeaturePRFCHW,
FeatureLZCNT,
@@ -963,6 +973,7 @@ def : ProcessorModel<"btver2", BtVer2Mod
FeatureFXSR,
FeatureNOPL,
FeatureSSE4A,
+ Feature64Bit,
FeatureCMPXCHG16B,
FeaturePRFCHW,
FeatureAES,
@@ -987,6 +998,7 @@ def : Proc<"bdver1", [
FeatureCMOV,
FeatureXOP,
FeatureFMA4,
+ Feature64Bit,
FeatureCMPXCHG16B,
FeatureAES,
FeaturePRFCHW,
@@ -1011,6 +1023,7 @@ def : Proc<"bdver2", [
FeatureCMOV,
FeatureXOP,
FeatureFMA4,
+ Feature64Bit,
FeatureCMPXCHG16B,
FeatureAES,
FeaturePRFCHW,
@@ -1040,6 +1053,7 @@ def : Proc<"bdver3", [
FeatureCMOV,
FeatureXOP,
FeatureFMA4,
+ Feature64Bit,
FeatureCMPXCHG16B,
FeatureAES,
FeaturePRFCHW,
@@ -1075,6 +1089,7 @@ def : Proc<"bdver4", [
FeatureNOPL,
FeatureXOP,
FeatureFMA4,
+ Feature64Bit,
FeatureCMPXCHG16B,
FeatureAES,
FeaturePRFCHW,
@@ -1107,6 +1122,7 @@ def: ProcessorModel<"znver1", Znver1Mode
FeatureCLFLUSHOPT,
FeatureCLZERO,
FeatureCMOV,
+ Feature64Bit,
FeatureCMPXCHG16B,
FeatureF16C,
FeatureFMA,
Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=341022&r1=341021&r2=341022&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Wed Aug 29 23:01:05 2018
@@ -230,14 +230,22 @@ void X86Subtarget::initSubtargetFeatures
if (CPUName.empty())
CPUName = "generic";
- // Make sure 64-bit features are available in 64-bit mode. (But make sure
- // SSE2 can be turned off explicitly.)
std::string FullFS = FS;
if (In64BitMode) {
+ // SSE2 should default to enabled in 64-bit mode, but can be turned off
+ // explicitly.
if (!FullFS.empty())
- FullFS = "+64bit,+sse2," + FullFS;
+ FullFS = "+sse2," + FullFS;
else
- FullFS = "+64bit,+sse2";
+ FullFS = "+sse2";
+
+ // If no CPU was specified, enable 64bit feature to satisy later check.
+ if (CPUName == "generic") {
+ if (!FullFS.empty())
+ FullFS = "+64bit," + FullFS;
+ else
+ FullFS = "+64bit";
+ }
}
// LAHF/SAHF are always supported in non-64-bit mode.
@@ -272,8 +280,9 @@ void X86Subtarget::initSubtargetFeatures
LLVM_DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel
<< ", 3DNowLevel " << X863DNowLevel << ", 64bit "
<< HasX86_64 << "\n");
- assert((!In64BitMode || HasX86_64) &&
- "64-bit code requested on a subtarget that doesn't support it!");
+ if (In64BitMode && !HasX86_64)
+ report_fatal_error("64-bit code requested on a subtarget that doesn't "
+ "support it!");
// Stack alignment is 16 bytes on Darwin, Linux, kFreeBSD and Solaris (both
// 32 and 64 bit) and for all 64-bit targets.
Modified: llvm/trunk/test/CodeGen/X86/cpus.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/cpus.ll?rev=341022&r1=341021&r2=341022&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/cpus.ll (original)
+++ llvm/trunk/test/CodeGen/X86/cpus.ll Wed Aug 29 23:01:05 2018
@@ -2,7 +2,7 @@
;
; First ensure the error message matches what we expect.
; CHECK-ERROR: not a recognized processor for this target
-; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=foobar 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=foobar 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
;
; Now ensure the error message doesn't occur for valid CPUs.
; CHECK-NO-ERROR-NOT: not a recognized processor for this target
@@ -27,8 +27,9 @@
; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium4 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium4m 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=yonah 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=prescott 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=lakemont 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
-; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=prescott 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=nocona 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=core2 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=penryn 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
@@ -55,7 +56,6 @@
; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=goldmont 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=goldmont-plus 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=tremont 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
-; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=lakemont 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=knl 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=knm 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
@@ -98,3 +98,40 @@
; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=winchip2 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=c3 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=c3-2 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+
+
+; Check that we reject 64-bit mode on 32-bit only CPUs.
+; CHECK-ERROR64: LLVM ERROR: 64-bit code requested on a subtarget that doesn't support it!
+; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=i386 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64
+; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=i486 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64
+; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=i586 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64
+; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=pentium 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64
+; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=pentium-mmx 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64
+; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=i686 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64
+; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=pentiumpro 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64
+; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=pentium2 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64
+; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=pentium3 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64
+; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=pentium3m 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64
+; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=pentium-m 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64
+; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=pentium4 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64
+; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=pentium4m 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64
+; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=yonah 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64
+; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=prescott 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64
+; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=lakemont 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64
+; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=k6 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64
+; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=k6-2 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64
+; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=k6-3 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64
+; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=athlon 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64
+; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=athlon-tbird 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64
+; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=athlon-4 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64
+; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=athlon-xp 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64
+; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=athlon-mp 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64
+; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=geode 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64
+; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=winchip-c6 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64
+; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=winchip2 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64
+; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=c3 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64
+; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=c3-2 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR
+
+define void @foo() {
+ ret void
+}
Modified: llvm/trunk/test/CodeGen/X86/early-ifcvt-crash.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/early-ifcvt-crash.ll?rev=341022&r1=341021&r2=341022&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/early-ifcvt-crash.ll (original)
+++ llvm/trunk/test/CodeGen/X86/early-ifcvt-crash.ll Wed Aug 29 23:01:05 2018
@@ -1,7 +1,7 @@
; RUN: llc < %s -x86-early-ifcvt -verify-machineinstrs
; RUN: llc < %s -x86-early-ifcvt -stress-early-ifcvt -verify-machineinstrs
; CPU without a scheduling model:
-; RUN: llc < %s -x86-early-ifcvt -mcpu=pentium3 -verify-machineinstrs
+; RUN: llc < %s -x86-early-ifcvt -mcpu=k8 -verify-machineinstrs
;
; Run these tests with and without -stress-early-ifcvt to exercise heuristics.
;
Modified: llvm/trunk/test/CodeGen/X86/pr11985.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr11985.ll?rev=341022&r1=341021&r2=341022&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr11985.ll (original)
+++ llvm/trunk/test/CodeGen/X86/pr11985.ll Wed Aug 29 23:01:05 2018
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=prescott | FileCheck %s --check-prefix=PRESCOTT
+; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=nocona | FileCheck %s --check-prefix=PRESCOTT
; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=nehalem | FileCheck %s --check-prefix=NEHALEM
;;; TODO: (1) Some of the loads and stores are certainly unaligned and (2) the first load and first
Modified: llvm/trunk/test/CodeGen/X86/pr34080.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr34080.ll?rev=341022&r1=341021&r2=341022&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr34080.ll (original)
+++ llvm/trunk/test/CodeGen/X86/pr34080.ll Wed Aug 29 23:01:05 2018
@@ -2,7 +2,7 @@
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+sse2 | FileCheck %s --check-prefix=SSE2
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+sse2 -mcpu=x86-64 | FileCheck %s --check-prefix=SSE2-SCHEDULE
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+sse3 | FileCheck %s --check-prefix=SSE3
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+sse3 -mcpu=prescott | FileCheck %s --check-prefix=SSE3
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+sse3 -mcpu=nocona | FileCheck %s --check-prefix=SSE3
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx | FileCheck %s --check-prefix=AVX
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx -mcpu=sandybridge | FileCheck %s --check-prefix=AVX
Modified: llvm/trunk/test/CodeGen/X86/x86-64-double-shifts-var.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/x86-64-double-shifts-var.ll?rev=341022&r1=341021&r2=341022&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/x86-64-double-shifts-var.ll (original)
+++ llvm/trunk/test/CodeGen/X86/x86-64-double-shifts-var.ll Wed Aug 29 23:01:05 2018
@@ -1,8 +1,3 @@
-; RUN: llc < %s -mtriple=x86_64-- -mcpu=athlon | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-- -mcpu=athlon-tbird | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-- -mcpu=athlon-4 | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-- -mcpu=athlon-xp | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-- -mcpu=athlon-mp | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-- -mcpu=k8 | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-- -mcpu=opteron | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-- -mcpu=athlon64 | FileCheck %s
Modified: llvm/trunk/test/ThinLTO/X86/cache-config.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/ThinLTO/X86/cache-config.ll?rev=341022&r1=341021&r2=341022&view=diff
==============================================================================
--- llvm/trunk/test/ThinLTO/X86/cache-config.ll (original)
+++ llvm/trunk/test/ThinLTO/X86/cache-config.ll Wed Aug 29 23:01:05 2018
@@ -2,7 +2,7 @@
; RUN: opt -module-hash -module-summary %s -o %t.bc
; RUN: llvm-lto2 run -o %t.o %t.bc -cache-dir %t.cache -r=%t.bc,globalfunc,plx
-; RUN: llvm-lto2 run -o %t.o %t.bc -cache-dir %t.cache -r=%t.bc,globalfunc,plx -mcpu=yonah
+; RUN: llvm-lto2 run -o %t.o %t.bc -cache-dir %t.cache -r=%t.bc,globalfunc,plx -mcpu=core2
; RUN: llvm-lto2 run -o %t.o %t.bc -cache-dir %t.cache -r=%t.bc,globalfunc,plx -relax-elf-relocations
; RUN: llvm-lto2 run -o %t.o %t.bc -cache-dir %t.cache -r=%t.bc,globalfunc,plx -function-sections
; RUN: llvm-lto2 run -o %t.o %t.bc -cache-dir %t.cache -r=%t.bc,globalfunc,plx -data-sections
Modified: llvm/trunk/test/Transforms/LoopUnroll/X86/partial.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopUnroll/X86/partial.ll?rev=341022&r1=341021&r2=341022&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/LoopUnroll/X86/partial.ll (original)
+++ llvm/trunk/test/Transforms/LoopUnroll/X86/partial.ll Wed Aug 29 23:01:05 2018
@@ -1,5 +1,5 @@
; RUN: opt < %s -S -loop-unroll -mcpu=nehalem | FileCheck %s
-; RUN: opt < %s -S -loop-unroll -mcpu=core -unroll-runtime=0 | FileCheck -check-prefix=CHECK-NOUNRL %s
+; RUN: opt < %s -S -loop-unroll -unroll-runtime=0 | FileCheck -check-prefix=CHECK-NOUNRL %s
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
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