[PATCH] D35722: [DAGCombine] Improve (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) folding

Simon Pilgrim via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Aug 16 10:24:36 PDT 2018


RKSimon added inline comments.


================
Comment at: test/CodeGen/X86/combine-sra.ll:133-134
 ; AVX-NEXT:    retq
   %1 = ashr <4 x i32> %x, <i32  1, i32  5, i32 50, i32 27>
   %2 = ashr <4 x i32> %1, <i32 33, i32 10, i32 33, i32  0>
   ret <4 x i32> %2
----------------
spatel wrote:
> To provide better coverage, add (or adjust this) test where both of the component shifts are below bitwidth, but the sum exceeds bitwidth?
See @combine_vec_ashr_ashr2 above


Repository:
  rL LLVM

https://reviews.llvm.org/D35722





More information about the llvm-commits mailing list