[PATCH] D35722: [DAGCombine] Improve (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) folding

[Sanjay Patel via Phabricator via llvm-commits]

spatel added inline comments.


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Comment at: test/CodeGen/X86/combine-sra.ll:133-134
 ; AVX-NEXT:    retq
   %1 = ashr <4 x i32> %x, <i32  1, i32  5, i32 50, i32 27>
   %2 = ashr <4 x i32> %1, <i32 33, i32 10, i32 33, i32  0>
   ret <4 x i32> %2
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To provide better coverage, add (or adjust this) test where both of the component shifts are below bitwidth, but the sum exceeds bitwidth?


Repository:
  rL LLVM

https://reviews.llvm.org/D35722