[PATCH] D49531: [PowerPC] Enhance the selection(ISD::VSELECT) of vector type

[Zixuan Wu via Phabricator via llvm-commits]

wuzish added a comment.

Add some more detail explanation.



================
Comment at: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp:590
+      setOperationAction(ISD::VSELECT, VT, Promote);
+      AddPromotedToType (ISD::VSELECT, VT, MVT::v4i32);
       setOperationAction(ISD::SELECT_CC, VT, Promote);
----------------
efriedma wrote:
> I don't think Promote does the right thing here; VectorLegalizer::Promote on a VSELECT just bitcasts the operands/result, and the documentation for ISD::VSELECT say "The condition follows the BooleanContent format of the target."  So DAGCombine might transform it incorrectly in some cases involving v16i8 or v8i16.
> 
> Granted, I'm not sure DAGCombine actually does any relevant transforms on the condition of a VSELECT, but it seems like a bad idea to rely on that.
Well, for v16i8 the initial DAG is like this


```
SelectionDAG has 15 nodes:
  t0: ch = EntryToken
        t6: v16i8,ch = CopyFromReg t0, Register:v16i8 %2
        t8: v16i8,ch = CopyFromReg t0, Register:v16i8 %3
      **t10: v16i1 = setcc t6, t8, seteq:ch**
      t2: v16i8,ch = CopyFromReg t0, Register:v16i8 %0
      t4: v16i8,ch = CopyFromReg t0, Register:v16i8 %1
    t11: v16i8 = vselect t10, t2, t4
  t13: ch,glue = CopyToReg t0, Register:v16i8 $v2, t11
  t14: ch = PPCISD::RET_FLAG t13, Register:v16i8 $v2, t13:1
```

The setcc result type is v16i1, but legalize type phase will change it to v16i8 as you said that follow the BooleanContent format of the target. So it 's like blow.


```
  t0: ch = EntryToken
        t6: v16i8,ch = CopyFromReg t0, Register:v16i8 %2
        t8: v16i8,ch = CopyFromReg t0, Register:v16i8 %3
**      t15: v16i8 = setcc t6, t8, seteq:ch**
      t2: v16i8,ch = CopyFromReg t0, Register:v16i8 %0
      t4: v16i8,ch = CopyFromReg t0, Register:v16i8 %1
**    t16: v16i8 = vselect t15, t2, t4**
  t13: ch,glue = CopyToReg t0, Register:v16i8 $v2, t16
  t14: ch = PPCISD::RET_FLAG t13, Register:v16i8 $v2, t13:1
```

What promote does is just make v16i8 to v4i32 consistently or canonically, so that we can just write one single pattern in td file to select `vselect` since the xxsel instruction is suitable for all vector type like v16i8/v8i16 because it's bit selection.

After legalize operation phase:

```
 SelectionDAG has 19 nodes:
  t0: ch = EntryToken
            t6: v16i8,ch = CopyFromReg t0, Register:v16i8 %2
             t8: v16i8,ch = CopyFromReg t0, Register:v16i8 %3
           t15: v16i8 = setcc t6, t8, seteq:ch
 **        t17: v4i32 = bitcast t15**
           t2: v16i8,ch = CopyFromReg t0, Register:v16i8 %0
**        t18: v4i32 = bitcast t2**
           t4: v16i8,ch = CopyFromReg t0, Register:v16i8 %1
**        t19: v4i32 = bitcast t4**
 **      t20: v4i32 = vselect t17, t18, t19**
     t21: v16i8 = bitcast t20
   t13: ch,glue = CopyToReg t0, Register:v16i8 $v2, t21
   t14: ch = PPCISD::RET_FLAG t13, Register:v16i8 $v2, t13:1
```


Repository:
  rL LLVM

https://reviews.llvm.org/D49531