[PATCH] D49531: [PowerPC] Enhance the selection(ISD::VSELECT) of vector type

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


================
Comment at: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp:590
+      setOperationAction(ISD::VSELECT, VT, Promote);
+      AddPromotedToType (ISD::VSELECT, VT, MVT::v4i32);
       setOperationAction(ISD::SELECT_CC, VT, Promote);
----------------
I don't think Promote does the right thing here; VectorLegalizer::Promote on a VSELECT just bitcasts the operands/result, and the documentation for ISD::VSELECT say "The condition follows the BooleanContent format of the target."  So DAGCombine might transform it incorrectly in some cases involving v16i8 or v8i16.

Granted, I'm not sure DAGCombine actually does any relevant transforms on the condition of a VSELECT, but it seems like a bad idea to rely on that.


Repository:
  rL LLVM

https://reviews.llvm.org/D49531