[PATCH] D50401: [GISel]: Add Opcodes for a few Libm Intrinsics
Aditya Nandakumar via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 10 11:21:56 PDT 2018
aditya_nandakumar updated this revision to Diff 160155.
aditya_nandakumar added a comment.
Changed the name based on feedback.
https://reviews.llvm.org/D50401
Files:
include/llvm/Support/TargetOpcodes.def
include/llvm/Target/GenericOpcodes.td
lib/CodeGen/GlobalISel/IRTranslator.cpp
test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
Index: test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
===================================================================
--- test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
+++ test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
@@ -1408,6 +1408,26 @@
ret float %res
}
+declare float @llvm.trunc.f32(float)
+define float @test_libm_trunc(float %a) {
+; CHECK-LABEL: name: test_libm_trunc
+; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
+; CHECK: [[RES:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[A]]
+; CHECK: $s0 = COPY [[RES]]
+ %res = call float @llvm.trunc.f32(float %a)
+ ret float %res
+}
+
+declare float @llvm.round.f32(float)
+define float @test_libm_round(float %a) {
+; CHECK-LABEL: name: test_libm_round
+; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
+; CHECK: [[RES:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUND [[A]]
+; CHECK: $s0 = COPY [[RES]]
+ %res = call float @llvm.round.f32(float %a)
+ ret float %res
+}
+
declare i32 @llvm.ctlz.i32(i32, i1)
define i32 @test_ctlz_intrinsic_zero_not_undef(i32 %a) {
; CHECK-LABEL: name: test_ctlz_intrinsic_zero_not_undef
Index: lib/CodeGen/GlobalISel/IRTranslator.cpp
===================================================================
--- lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -851,6 +851,16 @@
.addDef(getOrCreateVReg(CI))
.addUse(getOrCreateVReg(*CI.getArgOperand(0)));
return true;
+ case Intrinsic::trunc:
+ MIRBuilder.buildInstr(TargetOpcode::G_INTRINSIC_TRUNC)
+ .addDef(getOrCreateVReg(CI))
+ .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
+ return true;
+ case Intrinsic::round:
+ MIRBuilder.buildInstr(TargetOpcode::G_INTRINSIC_ROUND)
+ .addDef(getOrCreateVReg(CI))
+ .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
+ return true;
case Intrinsic::fma:
MIRBuilder.buildInstr(TargetOpcode::G_FMA)
.addDef(getOrCreateVReg(CI))
Index: include/llvm/Target/GenericOpcodes.td
===================================================================
--- include/llvm/Target/GenericOpcodes.td
+++ include/llvm/Target/GenericOpcodes.td
@@ -512,6 +512,21 @@
let hasSideEffects = 0;
}
+//------------------------------------------------------------------------------
+// Opcodes for LLVM Intrinsics
+//------------------------------------------------------------------------------
+def G_INTRINSIC_TRUNC : GenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$src1);
+ let hasSideEffects = 0;
+}
+
+def G_INTRINSIC_ROUND : GenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$src1);
+ let hasSideEffects = 0;
+}
+
//------------------------------------------------------------------------------
// Memory ops
//------------------------------------------------------------------------------
Index: include/llvm/Support/TargetOpcodes.def
===================================================================
--- include/llvm/Support/TargetOpcodes.def
+++ include/llvm/Support/TargetOpcodes.def
@@ -268,6 +268,12 @@
/// COPY is the relevant instruction.
HANDLE_TARGET_OPCODE(G_BITCAST)
+/// INTRINSIC trunc intrinsic.
+HANDLE_TARGET_OPCODE(G_INTRINSIC_TRUNC)
+
+/// INTRINSIC round intrinsic.
+HANDLE_TARGET_OPCODE(G_INTRINSIC_ROUND)
+
/// Generic load (including anyext load)
HANDLE_TARGET_OPCODE(G_LOAD)
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