[PATCH] D50202: [AArch64] Fix assertion failure on widened f16 BUILD_VECTOR

[Sjoerd Meijer via Phabricator via llvm-commits]

SjoerdMeijer added inline comments.


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Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:6896
       Lane = DAG.getConstant(LowBits.getZExtValue(), dl, MVT::i32);
+    } else if (Lane.getNode()->isUndef()) {
+      Lane = DAG.getUNDEF(MVT::i32);
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Doesn't look like you're testing this; add a test for this?


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Comment at: test/CodeGen/AArch64/arm64-build-vector.ll:43
+
+; The lowering of an f16 BUILD_VECTOR attempts to optimize it by building an
+; equivalent integer vector and then BITCAST-ing the result. This case checks
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Nit: perhaps move some of these explanations to the implementation in NormalizeBuildVector? But definitely a brief explanation of the test would be good.


Repository:
  rL LLVM

https://reviews.llvm.org/D50202