[PATCH] D50202: [AArch64] Fix assertion failure on widened f16 BUILD_VECTOR
Bryan Chan via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 2 15:33:27 PDT 2018
bryanpkc created this revision.
bryanpkc added reviewers: SjoerdMeijer, t.p.northover.
Herald added a reviewer: javed.absar.
Herald added subscribers: llvm-commits, kristof.beyls.
Ensure that NormalizedBuildVector returns a BUILD_VECTOR with operands of the
same type. This fixes an assertion failure in VerifySDNode.
Repository:
rL LLVM
https://reviews.llvm.org/D50202
Files:
lib/Target/AArch64/AArch64ISelLowering.cpp
test/CodeGen/AArch64/arm64-build-vector.ll
Index: test/CodeGen/AArch64/arm64-build-vector.ll
===================================================================
--- test/CodeGen/AArch64/arm64-build-vector.ll
+++ test/CodeGen/AArch64/arm64-build-vector.ll
@@ -39,3 +39,18 @@
%shuffle.i = shufflevector <4 x i16> %vshl_n2, <4 x i16> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
ret <8 x i16> %shuffle.i
}
+
+; The lowering of an f16 BUILD_VECTOR attempts to optimize it by building an
+; equivalent integer vector and then BITCAST-ing the result. This case checks
+; that the resulting normalized BUILD_VECTOR contains operands of the same
+; type, even when the BUILD_VECTOR has been widened. The choice of the
+; constant prevents earlier optimizations from replacing the BUILD_VECTOR.
+define void @widen_f16_build_vector(half* %addr) {
+; CHECK-LABEL: widen_f16_build_vector:
+; CHECK: mov w[[GREG:[0-9]+]], #13294
+; CHECK: dup.4h v0, w[[GREG]]
+; CHECK: str s0, [x0]
+ %1 = bitcast half* %addr to <2 x half>*
+ store <2 x half> <half 0xH33EE, half 0xH33EE>, <2 x half>* %1, align 2
+ ret void
+}
Index: lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- lib/Target/AArch64/AArch64ISelLowering.cpp
+++ lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -6893,6 +6893,10 @@
APInt LowBits(EltTy.getSizeInBits(),
CstLane->getZExtValue());
Lane = DAG.getConstant(LowBits.getZExtValue(), dl, MVT::i32);
+ } else if (Lane.getNode()->isUndef()) {
+ Lane = DAG.getUNDEF(MVT::i32);
+ } else if (Lane.getValueType().getSizeInBits() < 32) {
+ Lane = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Lane);
}
Ops.push_back(Lane);
}
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