[llvm] r338811 - [X86] Autogenerate complete checks. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 2 21:49:41 PDT 2018
Author: ctopper
Date: Thu Aug 2 21:49:41 2018
New Revision: 338811
URL: http://llvm.org/viewvc/llvm-project?rev=338811&view=rev
Log:
[X86] Autogenerate complete checks. NFC
Modified:
llvm/trunk/test/CodeGen/X86/sha.ll
Modified: llvm/trunk/test/CodeGen/X86/sha.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sha.ll?rev=338811&r1=338810&r2=338811&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sha.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sha.ll Thu Aug 2 21:49:41 2018
@@ -1,139 +1,186 @@
-; RUN: llc < %s -mattr=+sha -mtriple=x86_64-unknown-unknown | FileCheck %s
-; RUN: not llc < %s -mtriple=x86_64-unknown-unknown
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mattr=+sha -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
+; RUN: llc < %s -mattr=+sha,+avx2 -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
declare <4 x i32> @llvm.x86.sha1rnds4(<4 x i32>, <4 x i32>, i8) nounwind readnone
define <4 x i32> @test_sha1rnds4rr(<4 x i32> %a, <4 x i32> %b) nounwind uwtable {
+; CHECK-LABEL: test_sha1rnds4rr:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sha1rnds4 $3, %xmm1, %xmm0
+; CHECK-NEXT: retq
entry:
%0 = tail call <4 x i32> @llvm.x86.sha1rnds4(<4 x i32> %a, <4 x i32> %b, i8 3)
ret <4 x i32> %0
- ; CHECK: test_sha1rnds4rr
- ; CHECK: sha1rnds4 $3, %xmm1, %xmm0
}
define <4 x i32> @test_sha1rnds4rm(<4 x i32> %a, <4 x i32>* %b) nounwind uwtable {
+; CHECK-LABEL: test_sha1rnds4rm:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sha1rnds4 $3, (%rdi), %xmm0
+; CHECK-NEXT: retq
entry:
%0 = load <4 x i32>, <4 x i32>* %b
%1 = tail call <4 x i32> @llvm.x86.sha1rnds4(<4 x i32> %a, <4 x i32> %0, i8 3)
ret <4 x i32> %1
- ; CHECK: test_sha1rnds4rm
- ; CHECK: sha1rnds4 $3, (%rdi), %xmm0
}
declare <4 x i32> @llvm.x86.sha1nexte(<4 x i32>, <4 x i32>) nounwind readnone
define <4 x i32> @test_sha1nexterr(<4 x i32> %a, <4 x i32> %b) nounwind uwtable {
+; CHECK-LABEL: test_sha1nexterr:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sha1nexte %xmm1, %xmm0
+; CHECK-NEXT: retq
entry:
%0 = tail call <4 x i32> @llvm.x86.sha1nexte(<4 x i32> %a, <4 x i32> %b)
ret <4 x i32> %0
- ; CHECK: test_sha1nexterr
- ; CHECK: sha1nexte %xmm1, %xmm0
}
define <4 x i32> @test_sha1nexterm(<4 x i32> %a, <4 x i32>* %b) nounwind uwtable {
+; CHECK-LABEL: test_sha1nexterm:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sha1nexte (%rdi), %xmm0
+; CHECK-NEXT: retq
entry:
%0 = load <4 x i32>, <4 x i32>* %b
%1 = tail call <4 x i32> @llvm.x86.sha1nexte(<4 x i32> %a, <4 x i32> %0)
ret <4 x i32> %1
- ; CHECK: test_sha1nexterm
- ; CHECK: sha1nexte (%rdi), %xmm0
}
declare <4 x i32> @llvm.x86.sha1msg1(<4 x i32>, <4 x i32>) nounwind readnone
define <4 x i32> @test_sha1msg1rr(<4 x i32> %a, <4 x i32> %b) nounwind uwtable {
+; CHECK-LABEL: test_sha1msg1rr:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sha1msg1 %xmm1, %xmm0
+; CHECK-NEXT: retq
entry:
%0 = tail call <4 x i32> @llvm.x86.sha1msg1(<4 x i32> %a, <4 x i32> %b)
ret <4 x i32> %0
- ; CHECK: test_sha1msg1rr
- ; CHECK: sha1msg1 %xmm1, %xmm0
}
define <4 x i32> @test_sha1msg1rm(<4 x i32> %a, <4 x i32>* %b) nounwind uwtable {
+; CHECK-LABEL: test_sha1msg1rm:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sha1msg1 (%rdi), %xmm0
+; CHECK-NEXT: retq
entry:
%0 = load <4 x i32>, <4 x i32>* %b
%1 = tail call <4 x i32> @llvm.x86.sha1msg1(<4 x i32> %a, <4 x i32> %0)
ret <4 x i32> %1
- ; CHECK: test_sha1msg1rm
- ; CHECK: sha1msg1 (%rdi), %xmm0
}
declare <4 x i32> @llvm.x86.sha1msg2(<4 x i32>, <4 x i32>) nounwind readnone
define <4 x i32> @test_sha1msg2rr(<4 x i32> %a, <4 x i32> %b) nounwind uwtable {
+; CHECK-LABEL: test_sha1msg2rr:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sha1msg2 %xmm1, %xmm0
+; CHECK-NEXT: retq
entry:
%0 = tail call <4 x i32> @llvm.x86.sha1msg2(<4 x i32> %a, <4 x i32> %b)
ret <4 x i32> %0
- ; CHECK: test_sha1msg2rr
- ; CHECK: sha1msg2 %xmm1, %xmm0
}
define <4 x i32> @test_sha1msg2rm(<4 x i32> %a, <4 x i32>* %b) nounwind uwtable {
+; CHECK-LABEL: test_sha1msg2rm:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sha1msg2 (%rdi), %xmm0
+; CHECK-NEXT: retq
entry:
%0 = load <4 x i32>, <4 x i32>* %b
%1 = tail call <4 x i32> @llvm.x86.sha1msg2(<4 x i32> %a, <4 x i32> %0)
ret <4 x i32> %1
- ; CHECK: test_sha1msg2rm
- ; CHECK: sha1msg2 (%rdi), %xmm0
}
declare <4 x i32> @llvm.x86.sha256rnds2(<4 x i32>, <4 x i32>, <4 x i32>) nounwind readnone
define <4 x i32> @test_sha256rnds2rr(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) nounwind uwtable {
+; SSE-LABEL: test_sha256rnds2rr:
+; SSE: # %bb.0: # %entry
+; SSE-NEXT: movaps %xmm0, %xmm3
+; SSE-NEXT: movaps %xmm2, %xmm0
+; SSE-NEXT: sha256rnds2 %xmm0, %xmm1, %xmm3
+; SSE-NEXT: movaps %xmm3, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_sha256rnds2rr:
+; AVX: # %bb.0: # %entry
+; AVX-NEXT: vmovaps %xmm0, %xmm3
+; AVX-NEXT: vmovaps %xmm2, %xmm0
+; AVX-NEXT: sha256rnds2 %xmm0, %xmm1, %xmm3
+; AVX-NEXT: vmovaps %xmm3, %xmm0
+; AVX-NEXT: retq
entry:
%0 = tail call <4 x i32> @llvm.x86.sha256rnds2(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c)
ret <4 x i32> %0
- ; CHECK: test_sha256rnds2rr
- ; CHECK: movaps %xmm0, [[xmm_TMP1:%xmm[1-9][0-9]?]]
- ; CHECK: movaps %xmm2, %xmm0
- ; CHECK: sha256rnds2 %xmm0, %xmm1, [[xmm_TMP1]]
}
define <4 x i32> @test_sha256rnds2rm(<4 x i32> %a, <4 x i32>* %b, <4 x i32> %c) nounwind uwtable {
+; SSE-LABEL: test_sha256rnds2rm:
+; SSE: # %bb.0: # %entry
+; SSE-NEXT: movaps %xmm0, %xmm2
+; SSE-NEXT: movaps %xmm1, %xmm0
+; SSE-NEXT: sha256rnds2 %xmm0, (%rdi), %xmm2
+; SSE-NEXT: movaps %xmm2, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_sha256rnds2rm:
+; AVX: # %bb.0: # %entry
+; AVX-NEXT: vmovaps %xmm0, %xmm2
+; AVX-NEXT: vmovaps %xmm1, %xmm0
+; AVX-NEXT: sha256rnds2 %xmm0, (%rdi), %xmm2
+; AVX-NEXT: vmovaps %xmm2, %xmm0
+; AVX-NEXT: retq
entry:
%0 = load <4 x i32>, <4 x i32>* %b
%1 = tail call <4 x i32> @llvm.x86.sha256rnds2(<4 x i32> %a, <4 x i32> %0, <4 x i32> %c)
ret <4 x i32> %1
- ; CHECK: test_sha256rnds2rm
- ; CHECK: movaps %xmm0, [[xmm_TMP2:%xmm[1-9][0-9]?]]
- ; CHECK: movaps %xmm1, %xmm0
- ; CHECK: sha256rnds2 %xmm0, (%rdi), [[xmm_TMP2]]
}
declare <4 x i32> @llvm.x86.sha256msg1(<4 x i32>, <4 x i32>) nounwind readnone
define <4 x i32> @test_sha256msg1rr(<4 x i32> %a, <4 x i32> %b) nounwind uwtable {
+; CHECK-LABEL: test_sha256msg1rr:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sha256msg1 %xmm1, %xmm0
+; CHECK-NEXT: retq
entry:
%0 = tail call <4 x i32> @llvm.x86.sha256msg1(<4 x i32> %a, <4 x i32> %b)
ret <4 x i32> %0
- ; CHECK: test_sha256msg1rr
- ; CHECK: sha256msg1 %xmm1, %xmm0
}
define <4 x i32> @test_sha256msg1rm(<4 x i32> %a, <4 x i32>* %b) nounwind uwtable {
+; CHECK-LABEL: test_sha256msg1rm:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sha256msg1 (%rdi), %xmm0
+; CHECK-NEXT: retq
entry:
%0 = load <4 x i32>, <4 x i32>* %b
%1 = tail call <4 x i32> @llvm.x86.sha256msg1(<4 x i32> %a, <4 x i32> %0)
ret <4 x i32> %1
- ; CHECK: test_sha256msg1rm
- ; CHECK: sha256msg1 (%rdi), %xmm0
}
declare <4 x i32> @llvm.x86.sha256msg2(<4 x i32>, <4 x i32>) nounwind readnone
define <4 x i32> @test_sha256msg2rr(<4 x i32> %a, <4 x i32> %b) nounwind uwtable {
+; CHECK-LABEL: test_sha256msg2rr:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sha256msg2 %xmm1, %xmm0
+; CHECK-NEXT: retq
entry:
%0 = tail call <4 x i32> @llvm.x86.sha256msg2(<4 x i32> %a, <4 x i32> %b)
ret <4 x i32> %0
- ; CHECK: test_sha256msg2rr
- ; CHECK: sha256msg2 %xmm1, %xmm0
}
define <4 x i32> @test_sha256msg2rm(<4 x i32> %a, <4 x i32>* %b) nounwind uwtable {
+; CHECK-LABEL: test_sha256msg2rm:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sha256msg2 (%rdi), %xmm0
+; CHECK-NEXT: retq
entry:
%0 = load <4 x i32>, <4 x i32>* %b
%1 = tail call <4 x i32> @llvm.x86.sha256msg2(<4 x i32> %a, <4 x i32> %0)
ret <4 x i32> %1
- ; CHECK: test_sha256msg2rm
- ; CHECK: sha256msg2 (%rdi), %xmm0
}
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