[PATCH] D50070: [X86] Improved sched models for X86 CMPXCHG* instructions

[Andrew V. Tischenko via Phabricator via llvm-commits]

avt77 added inline comments.


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Comment at: lib/Target/X86/X86InstrInfo.td:2083
 
-let SchedRW = [WriteALULd, WriteRMW], mayLoad = 1, mayStore = 1,
+let SchedRW = [WriteCMPXCHGLd, WriteRMW], mayLoad = 1, mayStore = 1,
     hasSideEffects = 0 in {
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craig.topper wrote:
> If I remember right from arithmetic instructions, this doesn't make the latency additive the way it should be. This should probably be just WriteCMPXCHGRMW implemented as a WriteSequence like we do for WriteALURMW
The given implementation is very similar to suggested WriteSequence (in fact it's the same) and keeps all current sched values w/o changes. Could we stay with the current implementation or it's better to re-implement it?


https://reviews.llvm.org/D50070