[PATCH] D50070: [X86] Improved sched models for X86 CMPXCHG* instructions

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: lib/Target/X86/X86InstrInfo.td:2083
 
-let SchedRW = [WriteALULd, WriteRMW], mayLoad = 1, mayStore = 1,
+let SchedRW = [WriteCMPXCHGLd, WriteRMW], mayLoad = 1, mayStore = 1,
     hasSideEffects = 0 in {
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If I remember right from arithmetic instructions, this doesn't make the latency additive the way it should be. This should probably be just WriteCMPXCHGRMW implemented as a WriteSequence like we do for WriteALURMW


https://reviews.llvm.org/D50070