[PATCH] D49562: [X86][SSE] Use ISD::MULHU for constant/non-zero ISD::SRL lowering (PR38151)
Simon Pilgrim via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 31 06:24:02 PDT 2018
RKSimon updated this revision to Diff 158236.
RKSimon edited the summary of this revision.
RKSimon added a comment.
Reinstated AVX512 support
Repository:
rL LLVM
https://reviews.llvm.org/D49562
Files:
lib/Target/X86/X86ISelLowering.cpp
test/CodeGen/X86/combine-sdiv.ll
test/CodeGen/X86/combine-shl.ll
test/CodeGen/X86/vector-shift-lshr-128.ll
test/CodeGen/X86/vector-shift-lshr-256.ll
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D49562.158236.patch
Type: text/x-patch
Size: 60200 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20180731/b738b9ff/attachment.bin>
More information about the llvm-commits
mailing list