[PATCH] D49562: [X86][SSE] Use ISD::MULHU for constant/non-zero ISD::SRL lowering (PR38151)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: lib/Target/X86/X86ISelLowering.cpp:23516
+  // TODO: Add support for the shift by zero special case.
+  if (Op.getOpcode() == ISD::SRL && !Subtarget.hasAVX512() && ConstantAmt &&
+      ((Subtarget.hasSSE41() && VT == MVT::v8i16) ||
----------------
craig.topper wrote:
> Why are we punting with hasAVX512(). We don't get a variable shift of words until hasBWI.
This was a leftover from the zero amount handling - AVX512 can more efficiently extend to D/Q types, shift then truncate. I'll update the patch.


Repository:
  rL LLVM

https://reviews.llvm.org/D49562