[llvm] r337986 - CodeGen: Cleanup regmask construction; NFC
Matthias Braun via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 25 17:27:47 PDT 2018
Author: matze
Date: Wed Jul 25 17:27:47 2018
New Revision: 337986
URL: http://llvm.org/viewvc/llvm-project?rev=337986&view=rev
Log:
CodeGen: Cleanup regmask construction; NFC
- Avoid duplication of regmask size calculation.
- Simplify allocateRegisterMask() call.
- Rename allocateRegisterMask() to allocateRegMask() to be consistent
with naming in MachineOperand.
Modified:
llvm/trunk/include/llvm/CodeGen/MachineFunction.h
llvm/trunk/include/llvm/CodeGen/MachineOperand.h
llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp
llvm/trunk/lib/CodeGen/MachineFunction.cpp
llvm/trunk/lib/CodeGen/RegUsageInfoCollector.cpp
llvm/trunk/lib/CodeGen/StackMapLivenessAnalysis.cpp
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Modified: llvm/trunk/include/llvm/CodeGen/MachineFunction.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineFunction.h?rev=337986&r1=337985&r2=337986&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineFunction.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineFunction.h Wed Jul 25 17:27:47 2018
@@ -709,13 +709,7 @@ public:
}
/// Allocate and initialize a register mask with @p NumRegister bits.
- uint32_t *allocateRegisterMask(unsigned NumRegister) {
- unsigned Size = (NumRegister + 31) / 32;
- uint32_t *Mask = Allocator.Allocate<uint32_t>(Size);
- for (unsigned i = 0; i != Size; ++i)
- Mask[i] = 0;
- return Mask;
- }
+ uint32_t *allocateRegMask();
/// allocateMemRefsArray - Allocate an array to hold MachineMemOperand
/// pointers. This array is owned by the MachineFunction.
Modified: llvm/trunk/include/llvm/CodeGen/MachineOperand.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineOperand.h?rev=337986&r1=337985&r2=337986&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineOperand.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineOperand.h Wed Jul 25 17:27:47 2018
@@ -616,6 +616,11 @@ public:
return Contents.RegMask;
}
+ /// Returns number of elements needed for a regmask array.
+ static unsigned getRegMaskSize(unsigned NumRegs) {
+ return (NumRegs + 31) / 32;
+ }
+
/// getRegLiveOut - Returns a bit mask of live-out registers.
const uint32_t *getRegLiveOut() const {
assert(isRegLiveOut() && "Wrong MachineOperand accessor");
Modified: llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp?rev=337986&r1=337985&r2=337986&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp (original)
+++ llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp Wed Jul 25 17:27:47 2018
@@ -1958,13 +1958,11 @@ bool MIParser::parseTargetIndexOperand(M
bool MIParser::parseCustomRegisterMaskOperand(MachineOperand &Dest) {
assert(Token.stringValue() == "CustomRegMask" && "Expected a custom RegMask");
- const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
- assert(TRI && "Expected target register info");
lex();
if (expectAndConsume(MIToken::lparen))
return true;
- uint32_t *Mask = MF.allocateRegisterMask(TRI->getNumRegs());
+ uint32_t *Mask = MF.allocateRegMask();
while (true) {
if (Token.isNot(MIToken::NamedRegister))
return error("expected a named register");
@@ -1987,9 +1985,7 @@ bool MIParser::parseCustomRegisterMaskOp
bool MIParser::parseLiveoutRegisterMaskOperand(MachineOperand &Dest) {
assert(Token.is(MIToken::kw_liveout));
- const auto *TRI = MF.getSubtarget().getRegisterInfo();
- assert(TRI && "Expected target register info");
- uint32_t *Mask = MF.allocateRegisterMask(TRI->getNumRegs());
+ uint32_t *Mask = MF.allocateRegMask();
lex();
if (expectAndConsume(MIToken::lparen))
return true;
Modified: llvm/trunk/lib/CodeGen/MachineFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineFunction.cpp?rev=337986&r1=337985&r2=337986&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineFunction.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineFunction.cpp Wed Jul 25 17:27:47 2018
@@ -486,6 +486,14 @@ const char *MachineFunction::createExter
return Dest;
}
+uint32_t *MachineFunction::allocateRegMask() {
+ unsigned NumRegs = getSubtarget().getRegisterInfo()->getNumRegs();
+ unsigned Size = MachineOperand::getRegMaskSize(NumRegs);
+ uint32_t *Mask = Allocator.Allocate<uint32_t>(Size);
+ memset(Mask, 0, Size * sizeof(Mask[0]));
+ return Mask;
+}
+
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
LLVM_DUMP_METHOD void MachineFunction::dump() const {
print(dbgs());
Modified: llvm/trunk/lib/CodeGen/RegUsageInfoCollector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegUsageInfoCollector.cpp?rev=337986&r1=337985&r2=337986&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegUsageInfoCollector.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegUsageInfoCollector.cpp Wed Jul 25 17:27:47 2018
@@ -96,7 +96,7 @@ bool RegUsageInfoCollector::runOnMachine
// Compute the size of the bit vector to represent all the registers.
// The bit vector is broken into 32-bit chunks, thus takes the ceil of
// the number of registers divided by 32 for the size.
- unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32;
+ unsigned RegMaskSize = MachineOperand::getRegMaskSize(TRI->getNumRegs());
RegMask.resize(RegMaskSize, 0xFFFFFFFF);
const Function &F = MF.getFunction();
Modified: llvm/trunk/lib/CodeGen/StackMapLivenessAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/StackMapLivenessAnalysis.cpp?rev=337986&r1=337985&r2=337986&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/StackMapLivenessAnalysis.cpp (original)
+++ llvm/trunk/lib/CodeGen/StackMapLivenessAnalysis.cpp Wed Jul 25 17:27:47 2018
@@ -160,7 +160,7 @@ void StackMapLiveness::addLiveOutSetToMI
/// register live set.
uint32_t *StackMapLiveness::createRegisterMask(MachineFunction &MF) const {
// The mask is owned and cleaned up by the Machine Function.
- uint32_t *Mask = MF.allocateRegisterMask(TRI->getNumRegs());
+ uint32_t *Mask = MF.allocateRegMask();
for (auto Reg : LiveRegs)
Mask[Reg / 32] |= 1U << (Reg % 32);
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=337986&r1=337985&r2=337986&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Jul 25 17:27:47 2018
@@ -3909,9 +3909,9 @@ X86TargetLowering::LowerCall(TargetLower
const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
// Allocate a new Reg Mask and copy Mask.
- RegMask = MF.allocateRegisterMask(TRI->getNumRegs());
- unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32;
- memcpy(RegMask, Mask, sizeof(uint32_t) * RegMaskSize);
+ RegMask = MF.allocateRegMask();
+ unsigned RegMaskSize = MachineOperand::getRegMaskSize(TRI->getNumRegs());
+ memcpy(RegMask, Mask, sizeof(RegMask[0]) * RegMaskSize);
// Make sure all sub registers of the argument registers are reset
// in the RegMask.
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