[PATCH] D49598: [SystemZ] Use tablegen loops in SchedModels

[Ulrich Weigand via Phabricator via llvm-commits]

uweigand added a comment.

A few more comments, LGTM with those changes.



================
Comment at: lib/Target/SystemZ/SystemZScheduleZ13.td:64
+    def : WriteRes<!cast<SchedWrite>("WLat"#L), []> { let Latency = L; }
+  }
 }
----------------
Braces here as well.


================
Comment at: lib/Target/SystemZ/SystemZScheduleZ13.td:97
   def : WriteRes<VecXsPm, [Z13_VecUnit]>;
   def : WriteRes<VecXsPm2,[Z13_VecUnit]> { let ResourceCycles = [2]; }
+
----------------
For consistency with the general definition, you should move those (except VecFDd) up in the loop as well.


================
Comment at: lib/Target/SystemZ/SystemZScheduleZ14.td:64
+    def : WriteRes<!cast<SchedWrite>("WLat"#L), []> { let Latency = L; }
+  }
 }
----------------
Same comment as for z13.


================
Comment at: lib/Target/SystemZ/SystemZScheduleZ14.td:97
   def : WriteRes<VecXsPm, [Z14_VecUnit]>;
   def : WriteRes<VecXsPm2,[Z14_VecUnit]> { let ResourceCycles = [2]; }
+
----------------
Same comment as for z13.


https://reviews.llvm.org/D49598