[PATCH] D49574: [CodeGen] Fix ICE in SelectionDAG::computeKnownBits

[Scott Linder via Phabricator via llvm-commits]

scott.linder added inline comments.


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Comment at: lib/CodeGen/SelectionDAG/TargetLowering.cpp:1488
     const APInt& Idx = cast<ConstantSDNode>(Op.getOperand(1))->getAPIntValue();
     if (Idx.uge(NumSrcElts - NumElts))
       break;
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In writing tests for this version of the code in TargetLowering, I noticed that the condition here is actually more strict than in the equivalent code in SelectionDAG. In this function the subsequent `zext` can never assert. I still believe my original patch is correct, and I believe this condition can be relaxed to just `ugt`, but the fact that the code differs makes me wonder why.

Can someone who is more familiar with the code see a reason for the different condition?


https://reviews.llvm.org/D49574