[PATCH] D49574: [CodeGen] Fix ICE in SelectionDAG::computeKnownBits

[Scott Linder via Phabricator via llvm-commits]

scott.linder created this revision.
scott.linder added reviewers: RKSimon, arsenm, bogner.
Herald added subscribers: llvm-commits, nhaehnle, wdng.

SelectionDAG::computeKnownBits asserts handling EXTRACT_SUBVECTOR when zero extending the demanded elements mask if it is already as long as the source vector.

One assumption with the fix is that it is valid for EXTRACT_SUBVECTOR to ask for the entire original vector, which appears valid from reading the code. The test is just for the absence of the assert, as there is nothing in the IR/DAG to check for.


Repository:
  rL LLVM

https://reviews.llvm.org/D49574

Files:
  lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  test/CodeGen/AMDGPU/extract-subvector-equal-length.ll


Index: test/CodeGen/AMDGPU/extract-subvector-equal-length.ll
===================================================================
--- /dev/null
+++ test/CodeGen/AMDGPU/extract-subvector-equal-length.ll
@@ -0,0 +1,22 @@
+; RUN: llc -march=amdgcn < %s
+
+; Test for ICE in SelectionDAG::computeKnownBits when visiting EXTRACT_SUBVECTOR
+; with equal length vector arguments.
+
+define <3 x i32> @quux() #0 {
+bb:
+  %tmp = shufflevector <4 x i8> <i8 1, i8 2, i8 3, i8 4>, <4 x i8> undef, <3 x i32> <i32 0, i32 1, i32 2>
+  %tmp1 = extractelement <3 x i8> %tmp, i64 0
+  %tmp2 = zext i8 %tmp1 to i32
+  %tmp3 = insertelement <3 x i32> undef, i32 %tmp2, i32 0
+  %tmp4 = extractelement <3 x i8> %tmp, i64 1
+  %tmp5 = zext i8 %tmp4 to i32
+  %tmp6 = insertelement <3 x i32> %tmp3, i32 %tmp5, i32 1
+  %tmp7 = extractelement <3 x i8> %tmp, i64 2
+  %tmp8 = zext i8 %tmp7 to i32
+  %tmp9 = insertelement <3 x i32> %tmp6, i32 %tmp8, i32 2
+  %tmp10 = lshr <3 x i32> %tmp9, <i32 1, i32 1, i32 1>
+  ret <3 x i32> %tmp10
+}
+
+attributes #0 = { noinline optnone }
Index: lib/CodeGen/SelectionDAG/SelectionDAG.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -2346,7 +2346,7 @@
     if (SubIdx && SubIdx->getAPIntValue().ule(NumSrcElts - NumElts)) {
       // Offset the demanded elts by the subvector index.
       uint64_t Idx = SubIdx->getZExtValue();
-      APInt DemandedSrc = DemandedElts.zext(NumSrcElts).shl(Idx);
+      APInt DemandedSrc = DemandedElts.zextOrSelf(NumSrcElts).shl(Idx);
       computeKnownBits(Src, Known, DemandedSrc, Depth + 1);
     } else {
       computeKnownBits(Src, Known, Depth + 1);
@@ -3505,7 +3505,7 @@
     if (SubIdx && SubIdx->getAPIntValue().ule(NumSrcElts - NumElts)) {
       // Offset the demanded elts by the subvector index.
       uint64_t Idx = SubIdx->getZExtValue();
-      APInt DemandedSrc = DemandedElts.zext(NumSrcElts).shl(Idx);
+      APInt DemandedSrc = DemandedElts.zextOrSelf(NumSrcElts).shl(Idx);
       return ComputeNumSignBits(Src, DemandedSrc, Depth + 1);
     }
     return ComputeNumSignBits(Src, Depth + 1);


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