[PATCH] D49436: [X86][BtVer2] correctly model the latency/throughput of LEA instructions.

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: lib/Target/X86/X86FixupLEAs.cpp:289
 /// where the base is EBP, RBP, or R13
 static inline bool hasInefficientLEABaseReg(const MachineOperand &Base,
                                             const MachineOperand &Index) {
----------------
Add a TODO explaining that this should move to the scheduler model variants at some point?


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Comment at: lib/Target/X86/X86SchedPredicates.td:16
+
+def ZeroIdiomPredicate : CheckSameRegOperand<1, 2>;
+
----------------
Add description comments to each predicate.


https://reviews.llvm.org/D49436