[PATCH] D49436: [X86][BtVer2] correctly model the latency/throughput of LEA instructions.

[Matt Davis via Phabricator via llvm-commits]

mattd added a comment.

I think it makes sense to have a separate patch for checkInvalidRegOperand.  I do like that idea in particular, it simplifies reading the tablegen sources.



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Comment at: utils/TableGen/PredicateExpander.cpp:50
+  OS << "MI" << (isByRef() ? "." : "->") << "getOperand(" << OpIndex
+     << ").getReg() " << (shouldNegate() ? "!= " : "== ") << "0";
+}
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I'm curious about the hardcoded value "0",  is the invalid register always 0 for all targets?


https://reviews.llvm.org/D49436