[PATCH] D49243: [X86] Improved sched models for X86 BT*rr instructions

[Andrew V. Tischenko via Phabricator via llvm-commits]

avt77 added a comment.

> http://www.agner.org/optimize/instruction_tables.pdf, page 202, "Intel Haswell", "List of instruction timings and μop breakdown" appears to list all the BT* as having latency of 1.

I mixed columns for latency and throughput: latency is missed.


https://reviews.llvm.org/D49243