[PATCH] D49243: [X86] Improved sched models for X86 BT*rr instructions

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: lib/Target/X86/X86SchedHaswell.td:632
 }
 def : InstRW<[HWWriteBTRSCmr], (instregex "BT(R|S|C)(16|32|64)mr")>;
 
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RKSimon wrote:
> @craig.topper @courbet @gchatelet  These look completely wrong (and BTmr above) - and Broadwell appears to be missing them as well - any suggestions for the bit tests memory cases?
Skylake doesn't even have an InstRW for them.

They're also missing from the copy of the database used by IACA that I have. I believe that's where Gadi got most of the info from. I wonder what IACA does if you feed it those instructions.


https://reviews.llvm.org/D49243