[llvm] r337163 - [Sparc] Generate ta 1 for the @llvm.debugtrap intrinsic

[Galina Kistanova via llvm-commits]

Hello Daniel,

This commit broke tests on one of our builders:
http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/10982

. . .
Failing Tests (1):
    LLVM :: CodeGen/SPARC/trap.ll

Please have a look?

Thanks

Galina

On Mon, Jul 16, 2018 at 5:16 AM, Daniel Cederman via llvm-commits <
llvm-commits at lists.llvm.org> wrote:

> Author: dcederman
> Date: Mon Jul 16 05:16:53 2018
> New Revision: 337163
>
> URL: http://llvm.org/viewvc/llvm-project?rev=337163&view=rev
> Log:
> [Sparc] Generate ta 1 for the @llvm.debugtrap intrinsic
>
> Summary: Software trap number one is the trap used for breakpoints
> in the Sparc ABI.
>
> Reviewers: jyknight, venkatra
>
> Reviewed By: jyknight
>
> Subscribers: fedor.sergeev, jrtc27, llvm-commits
>
> Differential Revision: https://reviews.llvm.org/D48637
>
> Modified:
>     llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
>     llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td
>     llvm/trunk/test/CodeGen/SPARC/trap.ll
>
> Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/
> Sparc/SparcISelLowering.cpp?rev=337163&r1=337162&r2=337163&view=diff
> ============================================================
> ==================
> --- llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Mon Jul 16 05:16:53
> 2018
> @@ -1727,6 +1727,7 @@ SparcTargetLowering::SparcTargetLowering
>    setOperationAction(ISD::VAARG             , MVT::Other, Custom);
>
>    setOperationAction(ISD::TRAP              , MVT::Other, Legal);
> +  setOperationAction(ISD::DEBUGTRAP         , MVT::Other, Legal);
>
>    // Use the default implementation.
>    setOperationAction(ISD::VACOPY            , MVT::Other, Expand);
>
> Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/
> Sparc/SparcInstrInfo.td?rev=337163&r1=337162&r2=337163&view=diff
> ============================================================
> ==================
> --- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td Mon Jul 16 05:16:53 2018
> @@ -1009,6 +1009,9 @@ let DecoderNamespace = "SparcV9", Decode
>  let isBarrier = 1, isTerminator = 1, rd = 0b01000, rs1 = 0, simm13 = 5 in
>    def TA5 : F3_2<0b10, 0b111010, (outs), (ins), "ta 5", [(trap)]>;
>
> +def : Pat<(debugtrap),
> +  (TRAPri (i32 G0), (i32 1), (i32 8))>;
> +
>  // Section B.28 - Read State Register Instructions
>  let rs2 = 0 in
>    def RDASR : F3_1<2, 0b101000,
>
> Modified: llvm/trunk/test/CodeGen/SPARC/trap.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/
> CodeGen/SPARC/trap.ll?rev=337163&r1=337162&r2=337163&view=diff
> ============================================================
> ==================
> --- llvm/trunk/test/CodeGen/SPARC/trap.ll (original)
> +++ llvm/trunk/test/CodeGen/SPARC/trap.ll Mon Jul 16 05:16:53 2018
> @@ -9,3 +9,13 @@ define void @test1() {
>  }
>
>  declare void @llvm.trap()
> +
> +; CHECK-LABEL: testdebugtrap:
> +; CHECK: ta 1 ! encoding: [0x91,0xd0,0x20,0x01]
> +define void @testdebugtrap() {
> +entry:
> +  call void @llvm.debugtrap()
> +  ret void
> +}
> +
> +declare void @llvm.debugtrap()
>
>
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