[PATCH] D49310: [llvm-mca][BtVer2] Teach how to identify dependency-breaking idioms.

[Andrea Di Biagio via Phabricator via llvm-commits]

andreadb created this revision.
andreadb added reviewers: RKSimon, spatel, craig.topper, lebedev.ri, mattd, courbet.
Herald added subscribers: gbedwell, tschuett.

This patch teaches llvm-mca how to identify dependency breaking instructions on btver2.

An example of dependency breaking instruction is the zero-idiom XOR (example: XOR %eax, %eax), which always generates zero regardless of the actual input register value.
Dependency breaking instructions don't have to wait on their input register operands before executing. This is because the result of the execution is known in advance (i.e. it is not dependent on the actual value of the input register).

Not all dependency breaking idioms are also zero-latency instructions. For example, CMPEQ %xmm1, %xmm1 sets %xmm1 to all-ones, and it is executed by a pipeline.

This patch adds a new method named `isDependencyBreaking()` to the MCInstrAnalysis interface. That method takes as input an instruction (i.e. MCInst) and a MCSubtargetInfo.
The default implementation of `isDependencyBreaking()` conservatively returns false for all instructions. Targets may override the default behavior, and return a value which better matches the subtarget processor behavior.

BtVer2 tests that have been affected by this change now return the expected number of instructions per cycle.

Please let me know if okay to commit.

-Andrea


https://reviews.llvm.org/D49310

Files:
  include/llvm/MC/MCInstrAnalysis.h
  lib/MC/MCInstrAnalysis.cpp
  lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
  test/tools/llvm-mca/X86/BtVer2/dependency-breaking-cmp.s
  test/tools/llvm-mca/X86/BtVer2/dependency-breaking-pcmpeq.s
  test/tools/llvm-mca/X86/BtVer2/dependency-breaking-sbb-2.s
  test/tools/llvm-mca/X86/BtVer2/one-idioms.s
  tools/llvm-mca/DispatchStage.cpp
  tools/llvm-mca/InstrBuilder.cpp
  tools/llvm-mca/Instruction.h

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