[PATCH] D48936: [X86][SSE] Prefer BLEND(SHL(v, c1), SHL(v, c2)) over MUL(v, c3)
Roman Lebedev via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sun Jul 8 09:46:37 PDT 2018
lebedev.ri added inline comments.
================
Comment at: test/CodeGen/X86/lower-vec-shift.ll:211-232
define <8 x i16> @test9(<8 x i16> %a) {
; SSE-LABEL: test9:
; SSE: # %bb.0:
-; SSE-NEXT: movdqa %xmm0, %xmm1
-; SSE-NEXT: psraw $3, %xmm1
; SSE-NEXT: movdqa {{.*#+}} xmm2 = [65535,0,65535,65535,65535,0,0,0]
-; SSE-NEXT: psraw $1, %xmm0
-; SSE-NEXT: pand %xmm2, %xmm0
-; SSE-NEXT: pandn %xmm1, %xmm2
-; SSE-NEXT: por %xmm2, %xmm0
+; SSE-NEXT: movdqa %xmm0, %xmm1
+; SSE-NEXT: pand %xmm2, %xmm1
+; SSE-NEXT: psraw $2, %xmm0
----------------
Subj only talks about `mul`, but this is `div`.
This is intended to be changed by this patch?
If yes, there is no `lshr` test as far as i can tell.
Repository:
rL LLVM
https://reviews.llvm.org/D48936
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