[PATCH] D48642: [Mips][FastISel] Do not duplicate condition while lowering branches

[Petar Jovanovic via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL336084: [Mips][FastISel] Do not duplicate condition while lowering branches (authored by petarj, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D48642?vs=153063&id=153680#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D48642

Files:
  llvm/trunk/lib/Target/Mips/MipsFastISel.cpp
  llvm/trunk/test/CodeGen/Mips/Fast-ISel/icmpbr1.ll


Index: llvm/trunk/test/CodeGen/Mips/Fast-ISel/icmpbr1.ll
===================================================================
--- llvm/trunk/test/CodeGen/Mips/Fast-ISel/icmpbr1.ll
+++ llvm/trunk/test/CodeGen/Mips/Fast-ISel/icmpbr1.ll
@@ -0,0 +1,28 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel=true -mcpu=mips32r2 \
+; RUN:     < %s -verify-machineinstrs | FileCheck %s
+
+
+define i32 @foobar(i32*) {
+bb0:
+; CHECK-LABEL: foobar:
+; CHECK:       # %bb.0: # %bb0
+; CHECK:        lw $[[REG0:[0-9]+]], 0($4)
+; CHECK-NEXT:   sltiu $[[REG1:[0-9]+]], $[[REG0]], 1
+; CHECK:        sw $[[REG1]], [[SPILL:[0-9]+]]($sp) # 4-byte Folded Spill
+  %1 = load  i32, i32* %0 , align 4
+  %2 = icmp eq i32 %1, 0
+  store atomic i32 0, i32* %0 monotonic, align 4
+  br label %bb1
+bb1:
+; CHECK:       # %bb.1: # %bb1
+; CHECK-NEXT:    lw $[[REG2:[0-9]+]], [[SPILL]]($sp) # 4-byte Folded Reload
+; CHECK-NEXT:    bgtz $[[REG2]], $BB0_3
+  br i1 %2, label %bb2, label %bb3
+bb2:
+; CHECK:         $BB0_3: # %bb2
+; CHECK-NEXT:    addiu $2, $zero, 1
+  ret i32 1
+bb3:
+  ret i32 0
+}
Index: llvm/trunk/lib/Target/Mips/MipsFastISel.cpp
===================================================================
--- llvm/trunk/lib/Target/Mips/MipsFastISel.cpp
+++ llvm/trunk/lib/Target/Mips/MipsFastISel.cpp
@@ -951,12 +951,9 @@
   //
   MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
   MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
-  BI->getCondition();
   // For now, just try the simplest case where it's fed by a compare.
   if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
-    unsigned CondReg = createResultReg(&Mips::GPR32RegClass);
-    if (!emitCmp(CondReg, CI))
-      return false;
+    unsigned CondReg = getRegForValue(CI);
     BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::BGTZ))
         .addReg(CondReg)
         .addMBB(TBB);


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