[llvm] r336051 - [X86] When combining load to BZHI, make sure we create the shift instruction with an i8 type.

[Roman Lebedev via llvm-commits]

Thanks!

On Sat, Jun 30, 2018 at 8:49 PM, Craig Topper via llvm-commits
<llvm-commits at lists.llvm.org> wrote:
> Author: ctopper
> Date: Sat Jun 30 10:49:42 2018
> New Revision: 336051
>
> URL: http://llvm.org/viewvc/llvm-project?rev=336051&view=rev
> Log:
> [X86] When combining load to BZHI, make sure we create the shift instruction with an i8 type.
>
> This combine runs pretty late and causes us to introduce a shift after the op legalization phase has run. We need to be sure we create the shift with the proper type for the shift amount. If we don't do this, we will still re-legalize the operation properly, but we won't get a chance to fully optimize the truncate that gets inserted.
>
> So this patch adds the necessary truncate when the shift is created. I've also narrowed the subtract that gets created to always be an i32 type. The truncate would have trigered SimplifyDemandedBits to optimize it anyway. But using a more appropriate VT here is free and saves an optimization step.
>
> Modified:
>     llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=336051&r1=336050&r2=336051&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sat Jun 30 10:49:42 2018
> @@ -34646,7 +34646,7 @@ static bool hasBZHI(const X86Subtarget &
>  // It's equivalent to performing bzhi (zero high bits) on the input, with the
>  // same index of the load.
>  static SDValue combineAndLoadToBZHI(SDNode *Node, SelectionDAG &DAG,
> -    const X86Subtarget &Subtarget) {
> +                                    const X86Subtarget &Subtarget) {
>    MVT VT = Node->getSimpleValueType(0);
>    SDLoc dl(Node);
>
> @@ -34701,15 +34701,16 @@ static SDValue combineAndLoadToBZHI(SDNo
>            // <- (and (srl 0xFFFFFFFF, (sub 32, idx)))
>            //    that will be replaced with one bzhi instruction.
>            SDValue Inp = (i == 0) ? Node->getOperand(1) : Node->getOperand(0);
> -          SDValue SizeC = DAG.getConstant(VT.getSizeInBits(), dl, VT);
> +          SDValue SizeC = DAG.getConstant(VT.getSizeInBits(), dl, MVT::i32);
>
>            // Get the Node which indexes into the array.
>            SDValue Index = getIndexFromUnindexedLoad(Ld);
>            if (!Index)
>              return SDValue();
> -          Index = DAG.getZExtOrTrunc(Index, dl, VT);
> +          Index = DAG.getZExtOrTrunc(Index, dl, MVT::i32);
>
> -          SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SizeC, Index);
> +          SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, SizeC, Index);
> +          Sub = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Sub);
>
>            SDValue AllOnes = DAG.getAllOnesConstant(dl, VT);
>            SDValue LShr = DAG.getNode(ISD::SRL, dl, VT, AllOnes, Sub);
>
>
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