[PATCH] D48706: [X86] Suppress load folding into and/or/xor if it will prevent matching btr/bts/btc.
Roman Lebedev via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 28 00:07:21 PDT 2018
lebedev.ri added a comment.
This looks reasonable, but i'm not familiar with that code.
================
Comment at: lib/Target/X86/X86ISelDAGToDAG.cpp:576
+ // BTC: (xor X, (shl 1, n))
+ if ((U->getOpcode() == ISD::OR || U->getOpcode() == ISD::XOR)) {
+ if (U->getOperand(0).getOpcode() == ISD::SHL &&
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Extra unneeded brackets
Repository:
rL LLVM
https://reviews.llvm.org/D48706
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