[llvm] r335722 - [llvm-mca] Avoid calling method update() on instructions that are already in the IS_READY state. NFCI
Andrea Di Biagio via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 27 04:17:07 PDT 2018
Author: adibiagio
Date: Wed Jun 27 04:17:07 2018
New Revision: 335722
URL: http://llvm.org/viewvc/llvm-project?rev=335722&view=rev
Log:
[llvm-mca] Avoid calling method update() on instructions that are already in the IS_READY state. NFCI
When promoting instructions from the wait queue to the ready queue, we should
check if an instruction has already reached the IS_READY state before
calling method update().
Modified:
llvm/trunk/tools/llvm-mca/Instruction.cpp
llvm/trunk/tools/llvm-mca/Instruction.h
llvm/trunk/tools/llvm-mca/Scheduler.cpp
Modified: llvm/trunk/tools/llvm-mca/Instruction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mca/Instruction.cpp?rev=335722&r1=335721&r2=335722&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-mca/Instruction.cpp (original)
+++ llvm/trunk/tools/llvm-mca/Instruction.cpp Wed Jun 27 04:17:07 2018
@@ -32,8 +32,10 @@ void ReadState::writeStartEvent(unsigned
--DependentWrites;
TotalCycles = std::max(TotalCycles, Cycles);
- if (!DependentWrites)
+ if (!DependentWrites) {
CyclesLeft = TotalCycles;
+ IsReady = !CyclesLeft;
+ }
}
void WriteState::onInstructionIssued() {
@@ -83,8 +85,10 @@ void ReadState::cycleEvent() {
if (CyclesLeft == UNKNOWN_CYCLES)
return;
- if (CyclesLeft)
+ if (CyclesLeft) {
--CyclesLeft;
+ IsReady = !CyclesLeft;
+ }
}
#ifndef NDEBUG
@@ -119,9 +123,7 @@ void Instruction::execute() {
}
void Instruction::update() {
- if (!isDispatched())
- return;
-
+ assert(isDispatched() && "Unexpected instruction stage found!");
if (llvm::all_of(Uses, [](const UniqueUse &Use) { return Use->isReady(); }))
Stage = IS_READY;
}
@@ -131,9 +133,14 @@ void Instruction::cycleEvent() {
return;
if (isDispatched()) {
- for (UniqueUse &Use : Uses)
+ bool IsReady = true;
+ for (UniqueUse &Use : Uses) {
Use->cycleEvent();
- update();
+ IsReady &= Use->isReady();
+ }
+
+ if (IsReady)
+ Stage = IS_READY;
return;
}
Modified: llvm/trunk/tools/llvm-mca/Instruction.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mca/Instruction.h?rev=335722&r1=335721&r2=335722&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-mca/Instruction.h (original)
+++ llvm/trunk/tools/llvm-mca/Instruction.h Wed Jun 27 04:17:07 2018
@@ -162,17 +162,16 @@ class ReadState {
// dependent writes (i.e. field DependentWrite) is zero, this value is
// propagated to field CyclesLeft.
unsigned TotalCycles;
+ // This field is set to true only if there are no dependent writes, and
+ // there are no `CyclesLeft' to wait.
+ bool IsReady;
public:
- bool isReady() const {
- if (DependentWrites)
- return false;
- return (CyclesLeft == UNKNOWN_CYCLES || CyclesLeft == 0);
- }
+ bool isReady() const { return IsReady; }
ReadState(const ReadDescriptor &Desc, unsigned RegID)
: RD(Desc), RegisterID(RegID), DependentWrites(0),
- CyclesLeft(UNKNOWN_CYCLES), TotalCycles(0) {}
+ CyclesLeft(UNKNOWN_CYCLES), TotalCycles(0), IsReady(true) {}
ReadState(const ReadState &Other) = delete;
ReadState &operator=(const ReadState &Other) = delete;
@@ -182,7 +181,10 @@ public:
void cycleEvent();
void writeStartEvent(unsigned Cycles);
- void setDependentWrites(unsigned Writes) { DependentWrites = Writes; }
+ void setDependentWrites(unsigned Writes) {
+ DependentWrites = Writes;
+ IsReady = !Writes;
+ }
};
/// A sequence of cycles.
Modified: llvm/trunk/tools/llvm-mca/Scheduler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mca/Scheduler.cpp?rev=335722&r1=335721&r2=335722&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-mca/Scheduler.cpp (original)
+++ llvm/trunk/tools/llvm-mca/Scheduler.cpp Wed Jun 27 04:17:07 2018
@@ -293,7 +293,8 @@ void Scheduler::promoteToReadyQueue(Smal
// Check if this instruction is now ready. In case, force
// a transition in state using method 'update()'.
- IS->update();
+ if (!IS->isReady())
+ IS->update();
const InstrDesc &Desc = IS->getDesc();
bool IsMemOp = Desc.MayLoad || Desc.MayStore;
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