[PATCH] D48580: [AArch64] Support reserving x1-7 registers.

[Petr Hosek via Phabricator via llvm-commits]

phosek added inline comments.


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Comment at: lib/Target/AArch64/AArch64.td:75
 
-def FeatureReserveX18 : SubtargetFeature<"reserve-x18", "ReserveX18", "true",
-                                         "Reserve X18, making it unavailable "
-                                         "as a GPR">;
-
-def FeatureReserveX20 : SubtargetFeature<"reserve-x20", "ReserveX20", "true",
-                                         "Reserve X20, making it unavailable "
-                                         "as a GPR">;
+foreach i = {1-7,18,20} in
+    def FeatureReserveX#i : SubtargetFeature<"reserve-x"#i, "ReserveXRegister["#i#"]", "true",
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Since you're already making this change, can we support reserving all 32 registers?


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Comment at: lib/Target/AArch64/AArch64RegisterInfo.cpp:413
+    {
+    int numReserved = 0;
+    for (size_t i = 0; i < AArch64::GPR64commonRegClass.getNumRegs(); ++i) {
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Just a nit, but this should be `NumReserved`.


================
Comment at: lib/Target/AArch64/AArch64Subtarget.h:135
+  // ReserveXRegister[i] - X#i is not available as a general purpose register.
+  bool ReserveXRegister[31];
 
----------------
Can we make this a `BitVector`?


Repository:
  rL LLVM

https://reviews.llvm.org/D48580